oesel.qsf

FPGA开发光盘各章节实例的设计工程与源码

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		oesel_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:24:19  DECEMBER 06, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 3.0
set_global_assignment -name BDF_FILE rd_contr.bdf
set_global_assignment -name BDF_FILE contrIQ.bdf
set_global_assignment -name VHDL_FILE oesel.vhd
set_global_assignment -name BDF_FILE indatamux.bdf
set_global_assignment -name VHDL_FILE rh_lpm_dff0.vhd
set_global_assignment -name VHDL_FILE subdiv2.vhd
set_global_assignment -name VHDL_FILE adddiv2.vhd
set_global_assignment -name VHDL_FILE rh_lpm_add_sub1.vhd
set_global_assignment -name VHDL_FILE rd_contract.vhd
set_global_assignment -name VHDL_FILE rh_lpm_mult0.vhd
set_global_assignment -name VHDL_FILE expand.vhd
set_global_assignment -name VHDL_FILE sw1_4.vhd
set_global_assignment -name BDF_FILE rader_hilbert.bdf
set_global_assignment -name VECTOR_TEXT_FILE rader_hilbert.vec
set_global_assignment -name VECTOR_WAVEFORM_FILE ad_end8.vwf

# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"

# Timing Assignments
# ==================
set_global_assignment -name DO_MIN_ANALYSIS ON
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<NONE>"
set_global_assignment -name FAMILY Stratix
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY oesel

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1S25F780C5
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<NONE>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"

# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPC2
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL "1 ns"

# Design Assistant Assignments
# ============================
set_global_assignment -name ASSG_CAT OFF
set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
set_global_assignment -name CLK_CAT OFF
set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
set_global_assignment -name CLK_RULE_INV_CLOCK OFF
set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
set_global_assignment -name CLK_RULE_MIX_EDGES OFF
set_global_assignment -name RESET_CAT OFF
set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name TIMING_CAT OFF
set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
set_global_assignment -name SIGNALRACE_CAT OFF
set_global_assignment -name ACLK_CAT OFF
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF