rader_hilbert.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

X3_cout[15] = CARRY(F1L8Q & !S2_result[15] & !X3_cout[14] # !F1L8Q & (!X3_cout[14] # !S2_result[15]));


--E1_inst29 is contrIQ:inst4|inst29
--operation mode is normal

E1_inst29_lut_out = E1_inst26;
E1_inst29 = DFFEA(E1_inst29_lut_out, clk, VCC, , , , );


--L1_conclk1 is rd_contract:inst22|conclk1
--operation mode is normal

L1_conclk1_lut_out = E1_inst29;
L1_conclk1 = DFFEA(L1_conclk1_lut_out, clk, VCC, , , , );


--L1L2 is rd_contract:inst22|i~0
--operation mode is normal

L1L2 = E1_inst29 & !L1_conclk1;


--X3_sout_node[14] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]
--operation mode is arithmetic

X3_sout_node[14]_carry_eqn = X3_cout[13];
X3_sout_node[14]_lut_out = F1L8Q $ S2_result[14] $ !X3_sout_node[14]_carry_eqn;
X3_sout_node[14] = DFFEA(X3_sout_node[14]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[14] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

X3_cout[14] = CARRY(F1L8Q & (S2_result[14] # !X3_cout[13]) # !F1L8Q & S2_result[14] & !X3_cout[13]);


--X3_sout_node[13] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]
--operation mode is arithmetic

X3_sout_node[13]_carry_eqn = X3_cout[12];
X3_sout_node[13]_lut_out = F1L8Q $ S2_result[13] $ X3_sout_node[13]_carry_eqn;
X3_sout_node[13] = DFFEA(X3_sout_node[13]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[13] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

X3_cout[13] = CARRY(F1L8Q & !S2_result[13] & !X3_cout[12] # !F1L8Q & (!X3_cout[12] # !S2_result[13]));


--X3_sout_node[12] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]
--operation mode is arithmetic

X3_sout_node[12]_carry_eqn = X3_cout[11];
X3_sout_node[12]_lut_out = F1L8Q $ S2_result[12] $ !X3_sout_node[12]_carry_eqn;
X3_sout_node[12] = DFFEA(X3_sout_node[12]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[12] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

X3_cout[12] = CARRY(F1L8Q & (S2_result[12] # !X3_cout[11]) # !F1L8Q & S2_result[12] & !X3_cout[11]);


--X3_sout_node[11] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]
--operation mode is arithmetic

X3_sout_node[11]_carry_eqn = X3_cout[10];
X3_sout_node[11]_lut_out = F1L8Q $ S2_result[11] $ X3_sout_node[11]_carry_eqn;
X3_sout_node[11] = DFFEA(X3_sout_node[11]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[11] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

X3_cout[11] = CARRY(F1L8Q & !S2_result[11] & !X3_cout[10] # !F1L8Q & (!X3_cout[10] # !S2_result[11]));


--X3_sout_node[10] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]
--operation mode is arithmetic

X3_sout_node[10]_carry_eqn = X3_cout[9];
X3_sout_node[10]_lut_out = F1L8Q $ S2_result[10] $ !X3_sout_node[10]_carry_eqn;
X3_sout_node[10] = DFFEA(X3_sout_node[10]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[10] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

X3_cout[10] = CARRY(F1L8Q & (S2_result[10] # !X3_cout[9]) # !F1L8Q & S2_result[10] & !X3_cout[9]);


--X3_sout_node[9] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]
--operation mode is arithmetic

X3_sout_node[9]_carry_eqn = X3_cout[8];
X3_sout_node[9]_lut_out = F1L8Q $ S2_result[9] $ X3_sout_node[9]_carry_eqn;
X3_sout_node[9] = DFFEA(X3_sout_node[9]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[9] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

X3_cout[9] = CARRY(F1L8Q & !S2_result[9] & !X3_cout[8] # !F1L8Q & (!X3_cout[8] # !S2_result[9]));


--X3_sout_node[8] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]
--operation mode is arithmetic

X3_sout_node[8]_carry_eqn = X3_cout[7];
X3_sout_node[8]_lut_out = F1L8Q $ S2_result[8] $ !X3_sout_node[8]_carry_eqn;
X3_sout_node[8] = DFFEA(X3_sout_node[8]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[8] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

X3_cout[8] = CARRY(F1L8Q & (S2_result[8] # !X3_cout[7]) # !F1L8Q & S2_result[8] & !X3_cout[7]);


--M1L2 is sw1_4:inst23|i~0
--operation mode is normal

M1L2 = M2_ad_clk1 & !C1L3Q;


--X81_sout_node[6] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]
--operation mode is arithmetic

X81_sout_node[6]_carry_eqn = X81_cout[5];
X81_sout_node[6]_lut_out = F2L8Q $ S1_result[22] $ !X81_sout_node[6]_carry_eqn;
X81_sout_node[6] = DFFEA(X81_sout_node[6]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[6] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

X81_cout[6] = CARRY(F2L8Q & (S1_result[22] # !X81_cout[5]) # !F2L8Q & S1_result[22] & !X81_cout[5]);


--X81_sout_node[5] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]
--operation mode is arithmetic

X81_sout_node[5]_carry_eqn = X81_cout[4];
X81_sout_node[5]_lut_out = F2L8Q $ S1_result[21] $ X81_sout_node[5]_carry_eqn;
X81_sout_node[5] = DFFEA(X81_sout_node[5]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[5] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

X81_cout[5] = CARRY(F2L8Q & !S1_result[21] & !X81_cout[4] # !F2L8Q & (!X81_cout[4] # !S1_result[21]));


--X81_sout_node[4] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

X81_sout_node[4]_carry_eqn = X81_cout[3];
X81_sout_node[4]_lut_out = F2L8Q $ S1_result[20] $ !X81_sout_node[4]_carry_eqn;
X81_sout_node[4] = DFFEA(X81_sout_node[4]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[4] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

X81_cout[4] = CARRY(F2L8Q & (S1_result[20] # !X81_cout[3]) # !F2L8Q & S1_result[20] & !X81_cout[3]);


--X81_sout_node[3] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

X81_sout_node[3]_carry_eqn = X81_cout[2];
X81_sout_node[3]_lut_out = F2L8Q $ S1_result[19] $ X81_sout_node[3]_carry_eqn;
X81_sout_node[3] = DFFEA(X81_sout_node[3]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[3] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

X81_cout[3] = CARRY(F2L8Q & !S1_result[19] & !X81_cout[2] # !F2L8Q & (!X81_cout[2] # !S1_result[19]));


--X81_sout_node[2] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

X81_sout_node[2]_carry_eqn = X81_cout[1];
X81_sout_node[2]_lut_out = F2L8Q $ S1_result[18] $ !X81_sout_node[2]_carry_eqn;
X81_sout_node[2] = DFFEA(X81_sout_node[2]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[2] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

X81_cout[2] = CARRY(F2L8Q & (S1_result[18] # !X81_cout[1]) # !F2L8Q & S1_result[18] & !X81_cout[1]);


--X81_sout_node[1] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

X81_sout_node[1]_carry_eqn = X81_cout[0];
X81_sout_node[1]_lut_out = F2L8Q $ S1_result[17] $ X81_sout_node[1]_carry_eqn;
X81_sout_node[1] = DFFEA(X81_sout_node[1]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[1] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

X81_cout[1] = CARRY(F2L8Q & !S1_result[17] & !X81_cout[0] # !F2L8Q & (!X81_cout[0] # !S1_result[17]));


--X81_sout_node[0] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

X81_sout_node[0]_lut_out = F2L8Q $ S1_result[16];
X81_sout_node[0] = DFFEA(X81_sout_node[0]_lut_out, clk, VCC, , !E1_inst9, , );

--X81_cout[0] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

X81_cout[0] = CARRY(F2L8Q & S1_result[16]);


--X21_sout_node[15] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]
--operation mode is arithmetic

X21_sout_node[15]_carry_eqn = X21_cout[14];
X21_sout_node[15]_lut_out = F2L8Q $ S1_result[15] $ X21_sout_node[15]_carry_eqn;
X21_sout_node[15] = DFFEA(X21_sout_node[15]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[15] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

X21_cout[15] = CARRY(F2L8Q & !S1_result[15] & !X21_cout[14] # !F2L8Q & (!X21_cout[14] # !S1_result[15]));


--L2L1 is rd_contract:inst25|i~0
--operation mode is normal

L2L1 = L1_conclk1 & !E1_inst29;


--X21_sout_node[14] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]
--operation mode is arithmetic

X21_sout_node[14]_carry_eqn = X21_cout[13];
X21_sout_node[14]_lut_out = F2L8Q $ S1_result[14] $ !X21_sout_node[14]_carry_eqn;
X21_sout_node[14] = DFFEA(X21_sout_node[14]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[14] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

X21_cout[14] = CARRY(F2L8Q & (S1_result[14] # !X21_cout[13]) # !F2L8Q & S1_result[14] & !X21_cout[13]);


--X21_sout_node[13] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]
--operation mode is arithmetic

X21_sout_node[13]_carry_eqn = X21_cout[12];
X21_sout_node[13]_lut_out = F2L8Q $ S1_result[13] $ X21_sout_node[13]_carry_eqn;
X21_sout_node[13] = DFFEA(X21_sout_node[13]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[13] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

X21_cout[13] = CARRY(F2L8Q & !S1_result[13] & !X21_cout[12] # !F2L8Q & (!X21_cout[12] # !S1_result[13]));


--X21_sout_node[12] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]
--operation mode is arithmetic

X21_sout_node[12]_carry_eqn = X21_cout[11];
X21_sout_node[12]_lut_out = F2L8Q $ S1_result[12] $ !X21_sout_node[12]_carry_eqn;
X21_sout_node[12] = DFFEA(X21_sout_node[12]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[12] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

X21_cout[12] = CARRY(F2L8Q & (S1_result[12] # !X21_cout[11]) # !F2L8Q & S1_result[12] & !X21_cout[11]);


--X21_sout_node[11] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]
--operation mode is arithmetic

X21_sout_node[11]_carry_eqn = X21_cout[10];
X21_sout_node[11]_lut_out = F2L8Q $ S1_result[11] $ X21_sout_node[11]_carry_eqn;
X21_sout_node[11] = DFFEA(X21_sout_node[11]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[11] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

X21_cout[11] = CARRY(F2L8Q & !S1_result[11] & !X21_cout[10] # !F2L8Q & (!X21_cout[10] # !S1_result[11]));


--X21_sout_node[10] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]
--operation mode is arithmetic

X21_sout_node[10]_carry_eqn = X21_cout[9];
X21_sout_node[10]_lut_out = F2L8Q $ S1_result[10] $ !X21_sout_node[10]_carry_eqn;
X21_sout_node[10] = DFFEA(X21_sout_node[10]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[10] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

X21_cout[10] = CARRY(F2L8Q & (S1_result[10] # !X21_cout[9]) # !F2L8Q & S1_result[10] & !X21_cout[9]);


--X21_sout_node[9] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]
--operation mode is arithmetic

X21_sout_node[9]_carry_eqn = X21_cout[8];
X21_sout_node[9]_lut_out = F2L8Q $ S1_result[9] $ X21_sout_node[9]_carry_eqn;
X21_sout_node[9] = DFFEA(X21_sout_node[9]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[9] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

X21_cout[9] = CARRY(F2L8Q & !S1_result[9] & !X21_cout[8] # !F2L8Q & (!X21_cout[8] # !S1_result[9]));


--X21_sout_node[8] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]
--operation mode is arithmetic

X21_sout_node[8]_carry_eqn = X21_cout[7];
X21_sout_node[8]_lut_out = F2L8Q $ S1_result[8] $ !X21_sout_node[8]_carry_eqn;
X21_sout_node[8] = DFFEA(X21_sout_node[8]_lut_out, clk, VCC, , !E1_inst9, , );

--X21_cout[8] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

X21_cout[8] = CARRY(F2L8Q & (S1_result[8] # !X21_cout[7]) # !F2L8Q & S1_result[8] & !X21_cout[7]);


--G1_inst9 is rd_contr:inst10|inst9
--operation mode is normal

G1_inst9_lut_out = C1_hlmux1;
G1_inst9 = DFFEA(G1_inst9_lut_out, clk, VCC, , , , );


--F1L8Q is expand:inst6|expout[31]~reg0
--operation mode is normal

F1L8Q_lut_out = Q6_dffs[15];
F1L8Q = DFFEA(F1L8Q_lut_out, clk, VCC, , , , );


--E1_inst26 is contrIQ:inst4|inst26
--operation mode is normal

E1_inst26_lut_out = E1_inst9;
E1_inst26 = DFFEA(E1_inst26_lut_out, clk, VCC, , , , );


--F2L8Q is expand:inst17|expout[31]~reg0
--operation mode is normal

F2L8Q_lut_out = Q4_dffs[15];
F2L8Q = DFFEA(F2L8Q_lut_out, clk, VCC, , , , );


--E1_inst9 is contrIQ:inst4|inst9
--operation mode is normal

E1_inst9_lut_out = M2_ad_clk1;
E1_inst9 = DFFEA(E1_inst9_lut_out, clk, VCC, , , , );


--Q6_dffs[15] is rh_lpm_dff0:inst14|lpm_ff:lpm_ff_component|dffs[15]
--operation mode is normal

Q6_dffs[15]_lut_out = Q1_dffs[15];
Q6_dffs[15] = DFFEA(Q6_dffs[15]_lut_out, !C1L3Q, VCC, , , , );


--Q4_dffs[15] is rh_lpm_dff0:inst12|lpm_ff:lpm_ff_comp