rader_hilbert.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

--L1L11Q is rd_contract:inst22|wconout[8]~reg0
--operation mode is arithmetic

L1L11Q_lut_out = X3_sout_node[16] $ X9_sout_node[0];
L1L11Q = DFFEA(L1L11Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[0] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

X6_cout[0] = CARRY(X3_sout_node[16] & X9_sout_node[0]);


--L1L01Q is rd_contract:inst22|wconout[7]~reg0
--operation mode is normal

L1L01Q_lut_out = X3_sout_node[15];
L1L01Q = DFFEA(L1L01Q_lut_out, clk, VCC, , L1L2, , );


--L1L9Q is rd_contract:inst22|wconout[6]~reg0
--operation mode is normal

L1L9Q_lut_out = X3_sout_node[14];
L1L9Q = DFFEA(L1L9Q_lut_out, clk, VCC, , L1L2, , );


--L1L8Q is rd_contract:inst22|wconout[5]~reg0
--operation mode is normal

L1L8Q_lut_out = X3_sout_node[13];
L1L8Q = DFFEA(L1L8Q_lut_out, clk, VCC, , L1L2, , );


--L1L7Q is rd_contract:inst22|wconout[4]~reg0
--operation mode is normal

L1L7Q_lut_out = X3_sout_node[12];
L1L7Q = DFFEA(L1L7Q_lut_out, clk, VCC, , L1L2, , );


--L1L6Q is rd_contract:inst22|wconout[3]~reg0
--operation mode is normal

L1L6Q_lut_out = X3_sout_node[11];
L1L6Q = DFFEA(L1L6Q_lut_out, clk, VCC, , L1L2, , );


--L1L5Q is rd_contract:inst22|wconout[2]~reg0
--operation mode is normal

L1L5Q_lut_out = X3_sout_node[10];
L1L5Q = DFFEA(L1L5Q_lut_out, clk, VCC, , L1L2, , );


--L1L4Q is rd_contract:inst22|wconout[1]~reg0
--operation mode is normal

L1L4Q_lut_out = X3_sout_node[9];
L1L4Q = DFFEA(L1L4Q_lut_out, clk, VCC, , L1L2, , );


--L1L3Q is rd_contract:inst22|wconout[0]~reg0
--operation mode is normal

L1L3Q_lut_out = X3_sout_node[8];
L1L3Q = DFFEA(L1L3Q_lut_out, clk, VCC, , L1L2, , );


--M1_cnt is sw1_4:inst23|cnt
--operation mode is normal

M1_cnt_lut_out = !M1_cnt;
M1_cnt = DFFEA(M1_cnt_lut_out, clk, VCC, , M1L2, , );


--M1L63 is sw1_4:inst23|temp[15]~0
--operation mode is normal

M1L63 = M2_ad_clk1 & !M1_cnt & !C1L3Q;


--L2L61Q is rd_contract:inst25|wconout[14]~reg0
--operation mode is arithmetic

L2L61Q_carry_eqn = X51_cout[5];
L2L61Q_lut_out = X81_sout_node[6] $ !L2L61Q_carry_eqn;
L2L61Q = DFFEA(L2L61Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[6] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

X51_cout[6] = CARRY(X81_sout_node[6] & !X51_cout[5]);


--L2L51Q is rd_contract:inst25|wconout[13]~reg0
--operation mode is arithmetic

L2L51Q_carry_eqn = X51_cout[4];
L2L51Q_lut_out = X81_sout_node[5] $ L2L51Q_carry_eqn;
L2L51Q = DFFEA(L2L51Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[5] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

X51_cout[5] = CARRY(!X51_cout[4] # !X81_sout_node[5]);


--L2L41Q is rd_contract:inst25|wconout[12]~reg0
--operation mode is arithmetic

L2L41Q_carry_eqn = X51_cout[3];
L2L41Q_lut_out = X81_sout_node[4] $ !L2L41Q_carry_eqn;
L2L41Q = DFFEA(L2L41Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[4] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

X51_cout[4] = CARRY(X81_sout_node[4] & !X51_cout[3]);


--L2L31Q is rd_contract:inst25|wconout[11]~reg0
--operation mode is arithmetic

L2L31Q_carry_eqn = X51_cout[2];
L2L31Q_lut_out = X81_sout_node[3] $ L2L31Q_carry_eqn;
L2L31Q = DFFEA(L2L31Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[3] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

X51_cout[3] = CARRY(!X51_cout[2] # !X81_sout_node[3]);


--L2L21Q is rd_contract:inst25|wconout[10]~reg0
--operation mode is arithmetic

L2L21Q_carry_eqn = X51_cout[1];
L2L21Q_lut_out = X81_sout_node[2] $ !L2L21Q_carry_eqn;
L2L21Q = DFFEA(L2L21Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[2] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

X51_cout[2] = CARRY(X81_sout_node[2] & !X51_cout[1]);


--L2L11Q is rd_contract:inst25|wconout[9]~reg0
--operation mode is arithmetic

L2L11Q_carry_eqn = X51_cout[0];
L2L11Q_lut_out = X81_sout_node[1] $ L2L11Q_carry_eqn;
L2L11Q = DFFEA(L2L11Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[1] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

X51_cout[1] = CARRY(!X51_cout[0] # !X81_sout_node[1]);


--L2L01Q is rd_contract:inst25|wconout[8]~reg0
--operation mode is arithmetic

L2L01Q_lut_out = X21_sout_node[16] $ X81_sout_node[0];
L2L01Q = DFFEA(L2L01Q_lut_out, clk, VCC, , L2L1, , );

--X51_cout[0] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

X51_cout[0] = CARRY(X21_sout_node[16] & X81_sout_node[0]);


--L2L9Q is rd_contract:inst25|wconout[7]~reg0
--operation mode is normal

L2L9Q_lut_out = X21_sout_node[15];
L2L9Q = DFFEA(L2L9Q_lut_out, clk, VCC, , L2L1, , );


--L2L8Q is rd_contract:inst25|wconout[6]~reg0
--operation mode is normal

L2L8Q_lut_out = X21_sout_node[14];
L2L8Q = DFFEA(L2L8Q_lut_out, clk, VCC, , L2L1, , );


--L2L7Q is rd_contract:inst25|wconout[5]~reg0
--operation mode is normal

L2L7Q_lut_out = X21_sout_node[13];
L2L7Q = DFFEA(L2L7Q_lut_out, clk, VCC, , L2L1, , );


--L2L6Q is rd_contract:inst25|wconout[4]~reg0
--operation mode is normal

L2L6Q_lut_out = X21_sout_node[12];
L2L6Q = DFFEA(L2L6Q_lut_out, clk, VCC, , L2L1, , );


--L2L5Q is rd_contract:inst25|wconout[3]~reg0
--operation mode is normal

L2L5Q_lut_out = X21_sout_node[11];
L2L5Q = DFFEA(L2L5Q_lut_out, clk, VCC, , L2L1, , );


--L2L4Q is rd_contract:inst25|wconout[2]~reg0
--operation mode is normal

L2L4Q_lut_out = X21_sout_node[10];
L2L4Q = DFFEA(L2L4Q_lut_out, clk, VCC, , L2L1, , );


--L2L3Q is rd_contract:inst25|wconout[1]~reg0
--operation mode is normal

L2L3Q_lut_out = X21_sout_node[9];
L2L3Q = DFFEA(L2L3Q_lut_out, clk, VCC, , L2L1, , );


--L2L2Q is rd_contract:inst25|wconout[0]~reg0
--operation mode is normal

L2L2Q_lut_out = X21_sout_node[8];
L2L2Q = DFFEA(L2L2Q_lut_out, clk, VCC, , L2L1, , );


--G1_inst12 is rd_contr:inst10|inst12
--operation mode is normal

G1_inst12_lut_out = G1_inst9;
G1_inst12 = DFFEA(G1_inst12_lut_out, clk, VCC, , , , );


--G1_inst3 is rd_contr:inst10|inst3
--operation mode is normal

G1_inst3_lut_out = G1_inst;
G1_inst3 = DFFEA(G1_inst3_lut_out, clk, VCC, , , , );


--G1_inst is rd_contr:inst10|inst
--operation mode is normal

G1_inst_lut_out = ad_end;
G1_inst = DFFEA(G1_inst_lut_out, clk, VCC, , , , );


--C1_hlmux1 is oesel:inst1|hlmux1
--operation mode is normal

C1_hlmux1_lut_out = G1_inst3 & !G1_inst;
C1_hlmux1 = DFFEA(C1_hlmux1_lut_out, clk, VCC, , , , );


--C1L2 is oesel:inst1|i~0
--operation mode is normal

C1L2 = G1_inst3 & !G1_inst & !C1_hlmux1;


--M2L3 is sw1_4:inst26|i~0
--operation mode is normal

M2L3 = C1L3Q & !M2_ad_clk1;


--X9_sout_node[6] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]
--operation mode is arithmetic

X9_sout_node[6]_carry_eqn = X9_cout[5];
X9_sout_node[6]_lut_out = F1L8Q $ S2_result[22] $ !X9_sout_node[6]_carry_eqn;
X9_sout_node[6] = DFFEA(X9_sout_node[6]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[6] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

X9_cout[6] = CARRY(F1L8Q & (S2_result[22] # !X9_cout[5]) # !F1L8Q & S2_result[22] & !X9_cout[5]);


--X9_sout_node[5] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]
--operation mode is arithmetic

X9_sout_node[5]_carry_eqn = X9_cout[4];
X9_sout_node[5]_lut_out = F1L8Q $ S2_result[21] $ X9_sout_node[5]_carry_eqn;
X9_sout_node[5] = DFFEA(X9_sout_node[5]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[5] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

X9_cout[5] = CARRY(F1L8Q & !S2_result[21] & !X9_cout[4] # !F1L8Q & (!X9_cout[4] # !S2_result[21]));


--X9_sout_node[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

X9_sout_node[4]_carry_eqn = X9_cout[3];
X9_sout_node[4]_lut_out = F1L8Q $ S2_result[20] $ !X9_sout_node[4]_carry_eqn;
X9_sout_node[4] = DFFEA(X9_sout_node[4]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

X9_cout[4] = CARRY(F1L8Q & (S2_result[20] # !X9_cout[3]) # !F1L8Q & S2_result[20] & !X9_cout[3]);


--X9_sout_node[3] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

X9_sout_node[3]_carry_eqn = X9_cout[2];
X9_sout_node[3]_lut_out = F1L8Q $ S2_result[19] $ X9_sout_node[3]_carry_eqn;
X9_sout_node[3] = DFFEA(X9_sout_node[3]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[3] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

X9_cout[3] = CARRY(F1L8Q & !S2_result[19] & !X9_cout[2] # !F1L8Q & (!X9_cout[2] # !S2_result[19]));


--X9_sout_node[2] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

X9_sout_node[2]_carry_eqn = X9_cout[1];
X9_sout_node[2]_lut_out = F1L8Q $ S2_result[18] $ !X9_sout_node[2]_carry_eqn;
X9_sout_node[2] = DFFEA(X9_sout_node[2]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[2] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

X9_cout[2] = CARRY(F1L8Q & (S2_result[18] # !X9_cout[1]) # !F1L8Q & S2_result[18] & !X9_cout[1]);


--X9_sout_node[1] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

X9_sout_node[1]_carry_eqn = X9_cout[0];
X9_sout_node[1]_lut_out = F1L8Q $ S2_result[17] $ X9_sout_node[1]_carry_eqn;
X9_sout_node[1] = DFFEA(X9_sout_node[1]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[1] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

X9_cout[1] = CARRY(F1L8Q & !S2_result[17] & !X9_cout[0] # !F1L8Q & (!X9_cout[0] # !S2_result[17]));


--X9_sout_node[0] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

X9_sout_node[0]_lut_out = F1L8Q $ S2_result[16];
X9_sout_node[0] = DFFEA(X9_sout_node[0]_lut_out, clk, VCC, , E1_inst9, , );

--X9_cout[0] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

X9_cout[0] = CARRY(F1L8Q & S2_result[16]);


--X3_sout_node[15] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]
--operation mode is arithmetic

X3_sout_node[15]_carry_eqn = X3_cout[14];
X3_sout_node[15]_lut_out = F1L8Q $ S2_result[15] $ X3_sout_node[15]_carry_eqn;
X3_sout_node[15] = DFFEA(X3_sout_node[15]_lut_out, clk, VCC, , E1_inst9, , );

--X3_cout[15] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic