rader_hilbert.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

--M1L5Q is sw1_4:inst23|outdata[2]~reg0
--operation mode is normal

M1L5Q_lut_out = M1_temp[2];
M1L5Q = DFFEA(M1L5Q_lut_out, clk, VCC, , , , );


--M1L4Q is sw1_4:inst23|outdata[1]~reg0
--operation mode is normal

M1L4Q_lut_out = M1_temp[1];
M1L4Q = DFFEA(M1L4Q_lut_out, clk, VCC, , , , );


--M1L3Q is sw1_4:inst23|outdata[0]~reg0
--operation mode is normal

M1L3Q_lut_out = M1_temp[0];
M1L3Q = DFFEA(M1L3Q_lut_out, clk, VCC, , , , );


--G1_inst20 is rd_contr:inst10|inst20
--operation mode is normal

G1_inst20_lut_out = G1_inst17;
G1_inst20 = DFFEA(G1_inst20_lut_out, clk, VCC, , , , );


--M2_temp[15] is sw1_4:inst26|temp[15]
--operation mode is normal

M2_temp[15]_lut_out = L1L81Q;
M2_temp[15] = DFFEA(M2_temp[15]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[14] is sw1_4:inst26|temp[14]
--operation mode is normal

M2_temp[14]_lut_out = L1L71Q;
M2_temp[14] = DFFEA(M2_temp[14]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[13] is sw1_4:inst26|temp[13]
--operation mode is normal

M2_temp[13]_lut_out = L1L61Q;
M2_temp[13] = DFFEA(M2_temp[13]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[12] is sw1_4:inst26|temp[12]
--operation mode is normal

M2_temp[12]_lut_out = L1L51Q;
M2_temp[12] = DFFEA(M2_temp[12]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[11] is sw1_4:inst26|temp[11]
--operation mode is normal

M2_temp[11]_lut_out = L1L41Q;
M2_temp[11] = DFFEA(M2_temp[11]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[10] is sw1_4:inst26|temp[10]
--operation mode is normal

M2_temp[10]_lut_out = L1L31Q;
M2_temp[10] = DFFEA(M2_temp[10]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[9] is sw1_4:inst26|temp[9]
--operation mode is normal

M2_temp[9]_lut_out = L1L21Q;
M2_temp[9] = DFFEA(M2_temp[9]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[8] is sw1_4:inst26|temp[8]
--operation mode is normal

M2_temp[8]_lut_out = L1L11Q;
M2_temp[8] = DFFEA(M2_temp[8]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[7] is sw1_4:inst26|temp[7]
--operation mode is normal

M2_temp[7]_lut_out = L1L01Q;
M2_temp[7] = DFFEA(M2_temp[7]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[6] is sw1_4:inst26|temp[6]
--operation mode is normal

M2_temp[6]_lut_out = L1L9Q;
M2_temp[6] = DFFEA(M2_temp[6]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[5] is sw1_4:inst26|temp[5]
--operation mode is normal

M2_temp[5]_lut_out = L1L8Q;
M2_temp[5] = DFFEA(M2_temp[5]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[4] is sw1_4:inst26|temp[4]
--operation mode is normal

M2_temp[4]_lut_out = L1L7Q;
M2_temp[4] = DFFEA(M2_temp[4]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[3] is sw1_4:inst26|temp[3]
--operation mode is normal

M2_temp[3]_lut_out = L1L6Q;
M2_temp[3] = DFFEA(M2_temp[3]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[2] is sw1_4:inst26|temp[2]
--operation mode is normal

M2_temp[2]_lut_out = L1L5Q;
M2_temp[2] = DFFEA(M2_temp[2]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[1] is sw1_4:inst26|temp[1]
--operation mode is normal

M2_temp[1]_lut_out = L1L4Q;
M2_temp[1] = DFFEA(M2_temp[1]_lut_out, clk, VCC, , M2L73, , );


--M2_temp[0] is sw1_4:inst26|temp[0]
--operation mode is normal

M2_temp[0]_lut_out = L1L3Q;
M2_temp[0] = DFFEA(M2_temp[0]_lut_out, clk, VCC, , M2L73, , );


--M1_temp[15] is sw1_4:inst23|temp[15]
--operation mode is normal

M1_temp[15]_lut_out = L2L71Q;
M1_temp[15] = DFFEA(M1_temp[15]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[14] is sw1_4:inst23|temp[14]
--operation mode is normal

M1_temp[14]_lut_out = L2L61Q;
M1_temp[14] = DFFEA(M1_temp[14]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[13] is sw1_4:inst23|temp[13]
--operation mode is normal

M1_temp[13]_lut_out = L2L51Q;
M1_temp[13] = DFFEA(M1_temp[13]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[12] is sw1_4:inst23|temp[12]
--operation mode is normal

M1_temp[12]_lut_out = L2L41Q;
M1_temp[12] = DFFEA(M1_temp[12]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[11] is sw1_4:inst23|temp[11]
--operation mode is normal

M1_temp[11]_lut_out = L2L31Q;
M1_temp[11] = DFFEA(M1_temp[11]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[10] is sw1_4:inst23|temp[10]
--operation mode is normal

M1_temp[10]_lut_out = L2L21Q;
M1_temp[10] = DFFEA(M1_temp[10]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[9] is sw1_4:inst23|temp[9]
--operation mode is normal

M1_temp[9]_lut_out = L2L11Q;
M1_temp[9] = DFFEA(M1_temp[9]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[8] is sw1_4:inst23|temp[8]
--operation mode is normal

M1_temp[8]_lut_out = L2L01Q;
M1_temp[8] = DFFEA(M1_temp[8]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[7] is sw1_4:inst23|temp[7]
--operation mode is normal

M1_temp[7]_lut_out = L2L9Q;
M1_temp[7] = DFFEA(M1_temp[7]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[6] is sw1_4:inst23|temp[6]
--operation mode is normal

M1_temp[6]_lut_out = L2L8Q;
M1_temp[6] = DFFEA(M1_temp[6]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[5] is sw1_4:inst23|temp[5]
--operation mode is normal

M1_temp[5]_lut_out = L2L7Q;
M1_temp[5] = DFFEA(M1_temp[5]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[4] is sw1_4:inst23|temp[4]
--operation mode is normal

M1_temp[4]_lut_out = L2L6Q;
M1_temp[4] = DFFEA(M1_temp[4]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[3] is sw1_4:inst23|temp[3]
--operation mode is normal

M1_temp[3]_lut_out = L2L5Q;
M1_temp[3] = DFFEA(M1_temp[3]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[2] is sw1_4:inst23|temp[2]
--operation mode is normal

M1_temp[2]_lut_out = L2L4Q;
M1_temp[2] = DFFEA(M1_temp[2]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[1] is sw1_4:inst23|temp[1]
--operation mode is normal

M1_temp[1]_lut_out = L2L3Q;
M1_temp[1] = DFFEA(M1_temp[1]_lut_out, clk, VCC, , M1L63, , );


--M1_temp[0] is sw1_4:inst23|temp[0]
--operation mode is normal

M1_temp[0]_lut_out = L2L2Q;
M1_temp[0] = DFFEA(M1_temp[0]_lut_out, clk, VCC, , M1L63, , );


--G1_inst17 is rd_contr:inst10|inst17
--operation mode is normal

G1_inst17_lut_out = G1_inst12;
G1_inst17 = DFFEA(G1_inst17_lut_out, clk, VCC, , , , );


--C1L3Q is oesel:inst1|odden~reg0
--operation mode is normal

C1L3Q_lut_out = !C1L3Q;
C1L3Q = DFFEA(C1L3Q_lut_out, clk, VCC, , C1L2, , );


--M2_ad_clk1 is sw1_4:inst26|ad_clk1
--operation mode is normal

M2_ad_clk1_lut_out = C1L3Q;
M2_ad_clk1 = DFFEA(M2_ad_clk1_lut_out, clk, VCC, , , , );


--M2_cnt is sw1_4:inst26|cnt
--operation mode is normal

M2_cnt_lut_out = !M2_cnt;
M2_cnt = DFFEA(M2_cnt_lut_out, clk, VCC, , M2L3, , );


--M2L73 is sw1_4:inst26|temp[15]~0
--operation mode is normal

M2L73 = C1L3Q & !M2_ad_clk1 & !M2_cnt;


--L1L71Q is rd_contract:inst22|wconout[14]~reg0
--operation mode is arithmetic

L1L71Q_carry_eqn = X6_cout[5];
L1L71Q_lut_out = X9_sout_node[6] $ !L1L71Q_carry_eqn;
L1L71Q = DFFEA(L1L71Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[6] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

X6_cout[6] = CARRY(X9_sout_node[6] & !X6_cout[5]);


--L1L61Q is rd_contract:inst22|wconout[13]~reg0
--operation mode is arithmetic

L1L61Q_carry_eqn = X6_cout[4];
L1L61Q_lut_out = X9_sout_node[5] $ L1L61Q_carry_eqn;
L1L61Q = DFFEA(L1L61Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[5] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

X6_cout[5] = CARRY(!X6_cout[4] # !X9_sout_node[5]);


--L1L51Q is rd_contract:inst22|wconout[12]~reg0
--operation mode is arithmetic

L1L51Q_carry_eqn = X6_cout[3];
L1L51Q_lut_out = X9_sout_node[4] $ !L1L51Q_carry_eqn;
L1L51Q = DFFEA(L1L51Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

X6_cout[4] = CARRY(X9_sout_node[4] & !X6_cout[3]);


--L1L41Q is rd_contract:inst22|wconout[11]~reg0
--operation mode is arithmetic

L1L41Q_carry_eqn = X6_cout[2];
L1L41Q_lut_out = X9_sout_node[3] $ L1L41Q_carry_eqn;
L1L41Q = DFFEA(L1L41Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[3] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

X6_cout[3] = CARRY(!X6_cout[2] # !X9_sout_node[3]);


--L1L31Q is rd_contract:inst22|wconout[10]~reg0
--operation mode is arithmetic

L1L31Q_carry_eqn = X6_cout[1];
L1L31Q_lut_out = X9_sout_node[2] $ !L1L31Q_carry_eqn;
L1L31Q = DFFEA(L1L31Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[2] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

X6_cout[2] = CARRY(X9_sout_node[2] & !X6_cout[1]);


--L1L21Q is rd_contract:inst22|wconout[9]~reg0
--operation mode is arithmetic

L1L21Q_carry_eqn = X6_cout[0];
L1L21Q_lut_out = X9_sout_node[1] $ L1L21Q_carry_eqn;
L1L21Q = DFFEA(L1L21Q_lut_out, clk, VCC, , L1L2, , );

--X6_cout[1] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

X6_cout[1] = CARRY(!X6_cout[0] # !X9_sout_node[1]);