rader_hilbert.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

S2L92 = S2_mac_mult2_result[28];

--S2L03 is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|mac_mult2~DATAOUT29
S2L03 = S2_mac_mult2_result[29];

--S2L13 is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|mac_mult2~DATAOUT30
S2L13 = S2_mac_mult2_result[30];

--S2L23 is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|mac_mult2~DATAOUT31
S2L23 = S2_mac_mult2_result[31];


--S2_result[0] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[0]
--DSP Block Operation Mode: Simple Multiplier (18-bit)
S2_result[0] = S2_mac_mult2;

--S2_result[1] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[1]
S2_result[1] = S2L2;

--S2_result[2] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[2]
S2_result[2] = S2L3;

--S2_result[3] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[3]
S2_result[3] = S2L4;

--S2_result[4] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[4]
S2_result[4] = S2L5;

--S2_result[5] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[5]
S2_result[5] = S2L6;

--S2_result[6] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[6]
S2_result[6] = S2L7;

--S2_result[7] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[7]
S2_result[7] = S2L8;

--S2_result[8] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[8]
S2_result[8] = S2L9;

--S2_result[9] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[9]
S2_result[9] = S2L01;

--S2_result[10] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[10]
S2_result[10] = S2L11;

--S2_result[11] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[11]
S2_result[11] = S2L21;

--S2_result[12] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[12]
S2_result[12] = S2L31;

--S2_result[13] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[13]
S2_result[13] = S2L41;

--S2_result[14] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[14]
S2_result[14] = S2L51;

--S2_result[15] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[15]
S2_result[15] = S2L61;

--S2_result[16] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[16]
S2_result[16] = S2L71;

--S2_result[17] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[17]
S2_result[17] = S2L81;

--S2_result[18] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[18]
S2_result[18] = S2L91;

--S2_result[19] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[19]
S2_result[19] = S2L02;

--S2_result[20] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[20]
S2_result[20] = S2L12;

--S2_result[21] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[21]
S2_result[21] = S2L22;

--S2_result[22] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[22]
S2_result[22] = S2L32;

--S2_result[23] is rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_u6q:auto_generated|result[23]
S2_result[23] = S2L42;


--X9_sout_node[7] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]
--operation mode is normal

X9_sout_node[7]_carry_eqn = X9_cout[6];
X9_sout_node[7]_lut_out = F1L8Q $ S2_result[23] $ X9_sout_node[7]_carry_eqn;
X9_sout_node[7] = DFFEA(X9_sout_node[7]_lut_out, clk, VCC, , E1_inst9, , );


--X3_sout_node[16] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[16]
--operation mode is normal

X3_sout_node[16]_carry_eqn = X3_cout[15];
X3_sout_node[16]_lut_out = !X3_sout_node[16]_carry_eqn;
X3_sout_node[16] = DFFEA(X3_sout_node[16]_lut_out, clk, VCC, , E1_inst9, , );


--X3_cout[7] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

X3_cout[7] = CARRY(F1L8Q & !S2_result[7] & !X3_cout[6] # !F1L8Q & (!X3_cout[6] # !S2_result[7]));


--X3_cout[6] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

X3_cout[6] = CARRY(F1L7Q & (S2_result[6] # !X3_cout[5]) # !F1L7Q & S2_result[6] & !X3_cout[5]);


--X3_cout[5] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

X3_cout[5] = CARRY(F1L6Q & !S2_result[5] & !X3_cout[4] # !F1L6Q & (!X3_cout[4] # !S2_result[5]));


--X3_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

X3_cout[4] = CARRY(F1L5Q & (S2_result[4] # !X3_cout[3]) # !F1L5Q & S2_result[4] & !X3_cout[3]);


--X3_cout[3] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

X3_cout[3] = CARRY(F1L4Q & !S2_result[3] & !X3_cout[2] # !F1L4Q & (!X3_cout[2] # !S2_result[3]));


--X3_cout[2] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

X3_cout[2] = CARRY(F1L3Q & (S2_result[2] # !X3_cout[1]) # !F1L3Q & S2_result[2] & !X3_cout[1]);


--X3_cout[1] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

X3_cout[1] = CARRY(F1L2Q & !S2_result[1] & !X3_cout[0] # !F1L2Q & (!X3_cout[0] # !S2_result[1]));


--X3_cout[0] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

X3_cout[0] = CARRY(F1L1Q & S2_result[0]);


--L1L81Q is rd_contract:inst22|wconout[15]~reg0
--operation mode is normal

L1L81Q_carry_eqn = X6_cout[6];
L1L81Q_lut_out = X9_sout_node[7] $ L1L81Q_carry_eqn;
L1L81Q = DFFEA(L1L81Q_lut_out, clk, VCC, , L1L2, , );


--G1_inst23 is rd_contr:inst10|inst23
--operation mode is normal

G1_inst23_lut_out = G1_inst20;
G1_inst23 = DFFEA(G1_inst23_lut_out, clk, VCC, , , , );


--M2L91Q is sw1_4:inst26|outdata[15]~reg0
--operation mode is normal

M2L91Q_lut_out = M2_temp[15];
M2L91Q = DFFEA(M2L91Q_lut_out, clk, VCC, , , , );


--M2L81Q is sw1_4:inst26|outdata[14]~reg0
--operation mode is normal

M2L81Q_lut_out = M2_temp[14];
M2L81Q = DFFEA(M2L81Q_lut_out, clk, VCC, , , , );


--M2L71Q is sw1_4:inst26|outdata[13]~reg0
--operation mode is normal

M2L71Q_lut_out = M2_temp[13];
M2L71Q = DFFEA(M2L71Q_lut_out, clk, VCC, , , , );


--M2L61Q is sw1_4:inst26|outdata[12]~reg0
--operation mode is normal

M2L61Q_lut_out = M2_temp[12];
M2L61Q = DFFEA(M2L61Q_lut_out, clk, VCC, , , , );


--M2L51Q is sw1_4:inst26|outdata[11]~reg0
--operation mode is normal

M2L51Q_lut_out = M2_temp[11];
M2L51Q = DFFEA(M2L51Q_lut_out, clk, VCC, , , , );


--M2L41Q is sw1_4:inst26|outdata[10]~reg0
--operation mode is normal

M2L41Q_lut_out = M2_temp[10];
M2L41Q = DFFEA(M2L41Q_lut_out, clk, VCC, , , , );


--M2L31Q is sw1_4:inst26|outdata[9]~reg0
--operation mode is normal

M2L31Q_lut_out = M2_temp[9];
M2L31Q = DFFEA(M2L31Q_lut_out, clk, VCC, , , , );


--M2L21Q is sw1_4:inst26|outdata[8]~reg0
--operation mode is normal

M2L21Q_lut_out = M2_temp[8];
M2L21Q = DFFEA(M2L21Q_lut_out, clk, VCC, , , , );


--M2L11Q is sw1_4:inst26|outdata[7]~reg0
--operation mode is normal

M2L11Q_lut_out = M2_temp[7];
M2L11Q = DFFEA(M2L11Q_lut_out, clk, VCC, , , , );


--M2L01Q is sw1_4:inst26|outdata[6]~reg0
--operation mode is normal

M2L01Q_lut_out = M2_temp[6];
M2L01Q = DFFEA(M2L01Q_lut_out, clk, VCC, , , , );


--M2L9Q is sw1_4:inst26|outdata[5]~reg0
--operation mode is normal

M2L9Q_lut_out = M2_temp[5];
M2L9Q = DFFEA(M2L9Q_lut_out, clk, VCC, , , , );


--M2L8Q is sw1_4:inst26|outdata[4]~reg0
--operation mode is normal

M2L8Q_lut_out = M2_temp[4];
M2L8Q = DFFEA(M2L8Q_lut_out, clk, VCC, , , , );


--M2L7Q is sw1_4:inst26|outdata[3]~reg0
--operation mode is normal

M2L7Q_lut_out = M2_temp[3];
M2L7Q = DFFEA(M2L7Q_lut_out, clk, VCC, , , , );


--M2L6Q is sw1_4:inst26|outdata[2]~reg0
--operation mode is normal

M2L6Q_lut_out = M2_temp[2];
M2L6Q = DFFEA(M2L6Q_lut_out, clk, VCC, , , , );


--M2L5Q is sw1_4:inst26|outdata[1]~reg0
--operation mode is normal

M2L5Q_lut_out = M2_temp[1];
M2L5Q = DFFEA(M2L5Q_lut_out, clk, VCC, , , , );


--M2L4Q is sw1_4:inst26|outdata[0]~reg0
--operation mode is normal

M2L4Q_lut_out = M2_temp[0];
M2L4Q = DFFEA(M2L4Q_lut_out, clk, VCC, , , , );


--M1L81Q is sw1_4:inst23|outdata[15]~reg0
--operation mode is normal

M1L81Q_lut_out = M1_temp[15];
M1L81Q = DFFEA(M1L81Q_lut_out, clk, VCC, , , , );


--M1L71Q is sw1_4:inst23|outdata[14]~reg0
--operation mode is normal

M1L71Q_lut_out = M1_temp[14];
M1L71Q = DFFEA(M1L71Q_lut_out, clk, VCC, , , , );


--M1L61Q is sw1_4:inst23|outdata[13]~reg0
--operation mode is normal

M1L61Q_lut_out = M1_temp[13];
M1L61Q = DFFEA(M1L61Q_lut_out, clk, VCC, , , , );


--M1L51Q is sw1_4:inst23|outdata[12]~reg0
--operation mode is normal

M1L51Q_lut_out = M1_temp[12];
M1L51Q = DFFEA(M1L51Q_lut_out, clk, VCC, , , , );


--M1L41Q is sw1_4:inst23|outdata[11]~reg0
--operation mode is normal

M1L41Q_lut_out = M1_temp[11];
M1L41Q = DFFEA(M1L41Q_lut_out, clk, VCC, , , , );


--M1L31Q is sw1_4:inst23|outdata[10]~reg0
--operation mode is normal

M1L31Q_lut_out = M1_temp[10];
M1L31Q = DFFEA(M1L31Q_lut_out, clk, VCC, , , , );


--M1L21Q is sw1_4:inst23|outdata[9]~reg0
--operation mode is normal

M1L21Q_lut_out = M1_temp[9];
M1L21Q = DFFEA(M1L21Q_lut_out, clk, VCC, , , , );


--M1L11Q is sw1_4:inst23|outdata[8]~reg0
--operation mode is normal

M1L11Q_lut_out = M1_temp[8];
M1L11Q = DFFEA(M1L11Q_lut_out, clk, VCC, , , , );


--M1L01Q is sw1_4:inst23|outdata[7]~reg0
--operation mode is normal

M1L01Q_lut_out = M1_temp[7];
M1L01Q = DFFEA(M1L01Q_lut_out, clk, VCC, , , , );


--M1L9Q is sw1_4:inst23|outdata[6]~reg0
--operation mode is normal

M1L9Q_lut_out = M1_temp[6];
M1L9Q = DFFEA(M1L9Q_lut_out, clk, VCC, , , , );


--M1L8Q is sw1_4:inst23|outdata[5]~reg0
--operation mode is normal

M1L8Q_lut_out = M1_temp[5];
M1L8Q = DFFEA(M1L8Q_lut_out, clk, VCC, , , , );


--M1L7Q is sw1_4:inst23|outdata[4]~reg0
--operation mode is normal

M1L7Q_lut_out = M1_temp[4];
M1L7Q = DFFEA(M1L7Q_lut_out, clk, VCC, , , , );


--M1L6Q is sw1_4:inst23|outdata[3]~reg0
--operation mode is normal

M1L6Q_lut_out = M1_temp[3];
M1L6Q = DFFEA(M1L6Q_lut_out, clk, VCC, , , , );