rader_hilbert_hier_info

FPGA开发光盘各章节实例的设计工程与源码

|rader_hilbert
adenddly6 <= rd_contr:inst10.adenddly6
ad_end => rd_contr:inst10.ad_end
clk => rd_contr:inst10.clk
clk => sw1_4:inst26.clk
clk => oesel:inst1.clk
clk => rd_contract:inst22.clk
clk => contrIQ:inst4.clk
clk => rh_lpm_add_sub1:inst19.clock
clk => expand:inst6.clk
clk => sw1_4:inst23.clk
clk => rd_contract:inst25.clk
clk => rh_lpm_add_sub1:inst21.clock
clk => expand:inst17.clk
In[0] <= sw1_4:inst26.outdata[0]
In[1] <= sw1_4:inst26.outdata[1]
In[2] <= sw1_4:inst26.outdata[2]
In[3] <= sw1_4:inst26.outdata[3]
In[4] <= sw1_4:inst26.outdata[4]
In[5] <= sw1_4:inst26.outdata[5]
In[6] <= sw1_4:inst26.outdata[6]
In[7] <= sw1_4:inst26.outdata[7]
In[8] <= sw1_4:inst26.outdata[8]
In[9] <= sw1_4:inst26.outdata[9]
In[10] <= sw1_4:inst26.outdata[10]
In[11] <= sw1_4:inst26.outdata[11]
In[12] <= sw1_4:inst26.outdata[12]
In[13] <= sw1_4:inst26.outdata[13]
In[14] <= sw1_4:inst26.outdata[14]
In[15] <= sw1_4:inst26.outdata[15]
xn[0] => indatamux:inst.xn[0]
xn[1] => indatamux:inst.xn[1]
xn[2] => indatamux:inst.xn[2]
xn[3] => indatamux:inst.xn[3]
xn[4] => indatamux:inst.xn[4]
xn[5] => indatamux:inst.xn[5]
xn[6] => indatamux:inst.xn[6]
xn[7] => indatamux:inst.xn[7]
xn[8] => indatamux:inst.xn[8]
xn[9] => indatamux:inst.xn[9]
xn[10] => indatamux:inst.xn[10]
xn[11] => indatamux:inst.xn[11]
xn[12] => indatamux:inst.xn[12]
xn[13] => indatamux:inst.xn[13]
xn[14] => indatamux:inst.xn[14]
xn[15] => indatamux:inst.xn[15]
Qn[0] <= sw1_4:inst23.outdata[0]
Qn[1] <= sw1_4:inst23.outdata[1]
Qn[2] <= sw1_4:inst23.outdata[2]
Qn[3] <= sw1_4:inst23.outdata[3]
Qn[4] <= sw1_4:inst23.outdata[4]
Qn[5] <= sw1_4:inst23.outdata[5]
Qn[6] <= sw1_4:inst23.outdata[6]
Qn[7] <= sw1_4:inst23.outdata[7]
Qn[8] <= sw1_4:inst23.outdata[8]
Qn[9] <= sw1_4:inst23.outdata[9]
Qn[10] <= sw1_4:inst23.outdata[10]
Qn[11] <= sw1_4:inst23.outdata[11]
Qn[12] <= sw1_4:inst23.outdata[12]
Qn[13] <= sw1_4:inst23.outdata[13]
Qn[14] <= sw1_4:inst23.outdata[14]
Qn[15] <= sw1_4:inst23.outdata[15]


|rader_hilbert|rd_contr:inst10
hlmux <= inst16.DB_MAX_OUTPUT_PORT_TYPE
clk => inst3.CLK
clk => inst.CLK
clk => inst23.CLK
clk => inst20.CLK
clk => inst17.CLK
clk => inst12.CLK
clk => inst9.CLK
clk => inst6.CLK
ad_end => inst.DATAIN
adenddly6 <= inst23.DB_MAX_OUTPUT_PORT_TYPE


|rader_hilbert|sw1_4:inst26
clk => temp[15].CLK
clk => temp[14].CLK
clk => temp[13].CLK
clk => temp[12].CLK
clk => temp[11].CLK
clk => temp[10].CLK
clk => temp[9].CLK
clk => temp[8].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => cnt.CLK
clk => outdata[15]~reg0.CLK
clk => outdata[14]~reg0.CLK
clk => outdata[13]~reg0.CLK
clk => outdata[12]~reg0.CLK
clk => outdata[11]~reg0.CLK
clk => outdata[10]~reg0.CLK
clk => outdata[9]~reg0.CLK
clk => outdata[8]~reg0.CLK
clk => outdata[7]~reg0.CLK
clk => outdata[6]~reg0.CLK
clk => outdata[5]~reg0.CLK
clk => outdata[4]~reg0.CLK
clk => outdata[3]~reg0.CLK
clk => outdata[2]~reg0.CLK
clk => outdata[1]~reg0.CLK
clk => outdata[0]~reg0.CLK
clk => ad_clk1.CLK
ad_clk => i~0.IN1
ad_clk => ad_clk1.DATAIN
indata[0] => temp[0].DATAIN
indata[1] => temp[1].DATAIN
indata[2] => temp[2].DATAIN
indata[3] => temp[3].DATAIN
indata[4] => temp[4].DATAIN
indata[5] => temp[5].DATAIN
indata[6] => temp[6].DATAIN
indata[7] => temp[7].DATAIN
indata[8] => temp[8].DATAIN
indata[9] => temp[9].DATAIN
indata[10] => temp[10].DATAIN
indata[11] => temp[11].DATAIN
indata[12] => temp[12].DATAIN
indata[13] => temp[13].DATAIN
indata[14] => temp[14].DATAIN
indata[15] => temp[15].DATAIN
outdata[0] <= outdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[1] <= outdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[2] <= outdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[3] <= outdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[4] <= outdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[5] <= outdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[6] <= outdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[7] <= outdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[8] <= outdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[9] <= outdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[10] <= outdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[11] <= outdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[12] <= outdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[13] <= outdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[14] <= outdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[15] <= outdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|rader_hilbert|oesel:inst1
clk => odden~reg0.CLK
clk => evenen~reg0.CLK
clk => latchcnt.CLK
clk => hlmux1.CLK
hlmux => i~0.IN1
hlmux => hlmux1.DATAIN
odden <= odden~reg0.DB_MAX_OUTPUT_PORT_TYPE
evenen <= evenen~reg0.DB_MAX_OUTPUT_PORT_TYPE


|rader_hilbert|rd_contract:inst22
clk => wconout[15]~reg0.CLK
clk => wconout[14]~reg0.CLK
clk => wconout[13]~reg0.CLK
clk => wconout[12]~reg0.CLK
clk => wconout[11]~reg0.CLK
clk => wconout[10]~reg0.CLK
clk => wconout[9]~reg0.CLK
clk => wconout[8]~reg0.CLK
clk => wconout[7]~reg0.CLK
clk => wconout[6]~reg0.CLK
clk => wconout[5]~reg0.CLK
clk => wconout[4]~reg0.CLK
clk => wconout[3]~reg0.CLK
clk => wconout[2]~reg0.CLK
clk => wconout[1]~reg0.CLK
clk => wconout[0]~reg0.CLK
clk => conclk1.CLK
conin[8] => wconout[0]~reg0.DATAIN
conin[9] => wconout[1]~reg0.DATAIN
conin[10] => wconout[2]~reg0.DATAIN
conin[11] => wconout[3]~reg0.DATAIN
conin[12] => wconout[4]~reg0.DATAIN
conin[13] => wconout[5]~reg0.DATAIN
conin[14] => wconout[6]~reg0.DATAIN
conin[15] => wconout[7]~reg0.DATAIN
conin[16] => wconout[8]~reg0.DATAIN
conin[17] => wconout[9]~reg0.DATAIN
conin[18] => wconout[10]~reg0.DATAIN
conin[19] => wconout[11]~reg0.DATAIN
conin[20] => wconout[12]~reg0.DATAIN
conin[21] => wconout[13]~reg0.DATAIN
conin[22] => wconout[14]~reg0.DATAIN
conin[23] => wconout[15]~reg0.DATAIN
conclk => i~0.IN1
conclk => conclk1.DATAIN
wconout[0] <= wconout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[1] <= wconout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[2] <= wconout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[3] <= wconout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[4] <= wconout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[5] <= wconout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[6] <= wconout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[7] <= wconout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[8] <= wconout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[9] <= wconout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[10] <= wconout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[11] <= wconout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[12] <= wconout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[13] <= wconout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[14] <= wconout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wconout[15] <= wconout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|rader_hilbert|contrIQ:inst4
Iaddclken <= inst9.DB_MAX_OUTPUT_PORT_TYPE
clk => inst9.CLK
clk => inst32.CLK
clk => inst19.CLK
clk => inst38.CLK
clk => inst29.CLK
clk => inst26.CLK
clk => inst41.CLK
clk => inst35.CLK
odden => inst32.DATAIN
Qaddclken3 <= inst19.DB_MAX_OUTPUT_PORT_TYPE
evenen => inst38.DATAIN
Iconclk <= inst29.DB_MAX_OUTPUT_PORT_TYPE
Qconclk <= inst41.DB_MAX_OUTPUT_PORT_TYPE


|rader_hilbert|rh_lpm_add_sub1:inst19
dataa[0] => lpm_add_sub:lpm_add_sub_component.dataa[0]
dataa[1] => lpm_add_sub:lpm_add_sub_component.dataa[1]
dataa[2] => lpm_add_sub:lpm_add_sub_component.dataa[2]
dataa[3] => lpm_add_sub:lpm_add_sub_component.dataa[3]
dataa[4] => lpm_add_sub:lpm_add_sub_component.dataa[4]
dataa[5] => lpm_add_sub:lpm_add_sub_component.dataa[5]
dataa[6] => lpm_add_sub:lpm_add_sub_component.dataa[6]
dataa[7] => lpm_add_sub:lpm_add_sub_component.dataa[7]
dataa[8] => lpm_add_sub:lpm_add_sub_component.dataa[8]
dataa[9] => lpm_add_sub:lpm_add_sub_component.dataa[9]
dataa[10] => lpm_add_sub:lpm_add_sub_component.dataa[10]
dataa[11] => lpm_add_sub:lpm_add_sub_component.dataa[11]
dataa[12] => lpm_add_sub:lpm_add_sub_component.dataa[12]
dataa[13] => lpm_add_sub:lpm_add_sub_component.dataa[13]
dataa[14] => lpm_add_sub:lpm_add_sub_component.dataa[14]
dataa[15] => lpm_add_sub:lpm_add_sub_component.dataa[15]
dataa[16] => lpm_add_sub:lpm_add_sub_component.dataa[16]
dataa[17] => lpm_add_sub:lpm_add_sub_component.dataa[17]
dataa[18] => lpm_add_sub:lpm_add_sub_component.dataa[18]
dataa[19] => lpm_add_sub:lpm_add_sub_component.dataa[19]
dataa[20] => lpm_add_sub:lpm_add_sub_component.dataa[20]
dataa[21] => lpm_add_sub:lpm_add_sub_component.dataa[21]
dataa[22] => lpm_add_sub:lpm_add_sub_component.dataa[22]
dataa[23] => lpm_add_sub:lpm_add_sub_component.dataa[23]
dataa[24] => lpm_add_sub:lpm_add_sub_component.dataa[24]
dataa[25] => lpm_add_sub:lpm_add_sub_component.dataa[25]
dataa[26] => lpm_add_sub:lpm_add_sub_component.dataa[26]
dataa[27] => lpm_add_sub:lpm_add_sub_component.dataa[27]
dataa[28] => lpm_add_sub:lpm_add_sub_component.dataa[28]
dataa[29] => lpm_add_sub:lpm_add_sub_component.dataa[29]
dataa[30] => lpm_add_sub:lpm_add_sub_component.dataa[30]
dataa[31] => lpm_add_sub:lpm_add_sub_component.dataa[31]
datab[0] => lpm_add_sub:lpm_add_sub_component.datab[0]
datab[1] => lpm_add_sub:lpm_add_sub_component.datab[1]
datab[2] => lpm_add_sub:lpm_add_sub_component.datab[2]
datab[3] => lpm_add_sub:lpm_add_sub_component.datab[3]
datab[4] => lpm_add_sub:lpm_add_sub_component.datab[4]
datab[5] => lpm_add_sub:lpm_add_sub_component.datab[5]
datab[6] => lpm_add_sub:lpm_add_sub_component.datab[6]
datab[7] => lpm_add_sub:lpm_add_sub_component.datab[7]
datab[8] => lpm_add_sub:lpm_add_sub_component.datab[8]
datab[9] => lpm_add_sub:lpm_add_sub_component.datab[9]
datab[10] => lpm_add_sub:lpm_add_sub_component.datab[10]
datab[11] => lpm_add_sub:lpm_add_sub_component.datab[11]
datab[12] => lpm_add_sub:lpm_add_sub_component.datab[12]
datab[13] => lpm_add_sub:lpm_add_sub_component.datab[13]
datab[14] => lpm_add_sub:lpm_add_sub_component.datab[14]
datab[15] => lpm_add_sub:lpm_add_sub_component.datab[15]
datab[16] => lpm_add_sub:lpm_add_sub_component.datab[16]
datab[17] => lpm_add_sub:lpm_add_sub_component.datab[17]
datab[18] => lpm_add_sub:lpm_add_sub_component.datab[18]
datab[19] => lpm_add_sub:lpm_add_sub_component.datab[19]
datab[20] => lpm_add_sub:lpm_add_sub_component.datab[20]
datab[21] => lpm_add_sub:lpm_add_sub_component.datab[21]
datab[22] => lpm_add_sub:lpm_add_sub_component.datab[22]
datab[23] => lpm_add_sub:lpm_add_sub_component.datab[23]
datab[24] => lpm_add_sub:lpm_add_sub_component.datab[24]
datab[25] => lpm_add_sub:lpm_add_sub_component.datab[25]
datab[26] => lpm_add_sub:lpm_add_sub_component.datab[26]
datab[27] => lpm_add_sub:lpm_add_sub_component.datab[27]
datab[28] => lpm_add_sub:lpm_add_sub_component.datab[28]
datab[29] => lpm_add_sub:lpm_add_sub_component.datab[29]
datab[30] => lpm_add_sub:lpm_add_sub_component.datab[30]
datab[31] => lpm_add_sub:lpm_add_sub_component.datab[31]
clock => lpm_add_sub:lpm_add_sub_component.clock
clken => lpm_add_sub:lpm_add_sub_component.clken
result[0] <= lpm_add_sub:lpm_add_sub_component.result[0]
result[1] <= lpm_add_sub:lpm_add_sub_component.result[1]
result[2] <= lpm_add_sub:lpm_add_sub_component.result[2]
result[3] <= lpm_add_sub:lpm_add_sub_component.result[3]
result[4] <= lpm_add_sub:lpm_add_sub_component.result[4]
result[5] <= lpm_add_sub:lpm_add_sub_component.result[5]
result[6] <= lpm_add_sub:lpm_add_sub_component.result[6]
result[7] <= lpm_add_sub:lpm_add_sub_component.result[7]
result[8] <= lpm_add_sub:lpm_add_sub_component.result[8]
result[9] <= lpm_add_sub:lpm_add_sub_component.result[9]
result[10] <= lpm_add_sub:lpm_add_sub_component.result[10]
result[11] <= lpm_add_sub:lpm_add_sub_component.result[11]
result[12] <= lpm_add_sub:lpm_add_sub_component.result[12]
result[13] <= lpm_add_sub:lpm_add_sub_component.result[13]
result[14] <= lpm_add_sub:lpm_add_sub_component.result[14]
result[15] <= lpm_add_sub:lpm_add_sub_component.result[15]
result[16] <= lpm_add_sub:lpm_add_sub_component.result[16]
result[17] <= lpm_add_sub:lpm_add_sub_component.result[17]
result[18] <= lpm_add_sub:lpm_add_sub_component.result[18]
result[19] <= lpm_add_sub:lpm_add_sub_component.result[19]
result[20] <= lpm_add_sub:lpm_add_sub_component.result[20]
result[21] <= lpm_add_sub:lpm_add_sub_component.result[21]
result[22] <= lpm_add_sub:lpm_add_sub_component.result[22]
result[23] <= lpm_add_sub:lpm_add_sub_component.result[23]
result[24] <= lpm_add_sub:lpm_add_sub_component.result[24]
result[25] <= lpm_add_sub:lpm_add_sub_component.result[25]
result[26] <= lpm_add_sub:lpm_add_sub_component.result[26]
result[27] <= lpm_add_sub:lpm_add_sub_component.result[27]
result[28] <= lpm_add_sub:lpm_add_sub_component.result[28]
result[29] <= lpm_add_sub:lpm_add_sub_component.result[29]
result[30] <= lpm_add_sub:lpm_add_sub_component.result[30]
result[31] <= lpm_add_sub:lpm_add_sub_component.result[31]


|rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component
dataa[0] => addcore:adder1[0].dataa[0]
dataa[1] => addcore:adder1[0].dataa[1]
dataa[2] => addcore:adder1[0].dataa[2]
dataa[3] => addcore:adder1[0].dataa[3]
dataa[4] => addcore:adder1[0].dataa[4]
dataa[5] => addcore:adder1[0].dataa[5]
dataa[6] => addcore:adder1[0].dataa[6]
dataa[7] => addcore:adder1[0].dataa[7]
dataa[8] => addcore:adder1[0].dataa[8]
dataa[9] => addcore:adder1[0].dataa[9]
dataa[10] => addcore:adder1[0].dataa[10]
dataa[11] => addcore:adder1[0].dataa[11]
dataa[12] => addcore:adder1[0].dataa[12]
dataa[13] => addcore:adder1[0].dataa[13]
dataa[14] => addcore:adder1[0].dataa[14]
dataa[15] => addcore:adder1[0].dataa[15]
dataa[16] => addcore:adder1_0[1].dataa[0]
dataa[17] => addcore:adder1_0[1].dataa[1]