rader_hilbert.fit.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "oesel:inst1\|evenen Global clock " "Info: Automatically promoted some destinations of signal \"oesel:inst1\|evenen\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "oesel:inst1\|evenen " "Info: Destination \"oesel:inst1\|evenen\" may be non-global or may not use global clock" {  } { { "oesel.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd" 11 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sw1_4:inst23\|ad_clk1 " "Info: Destination \"sw1_4:inst23\|ad_clk1\" may be non-global or may not use global clock" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sw1_4:inst26\|cnt " "Info: Destination \"sw1_4:inst26\|cnt\" may be non-global or may not use global clock" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 19 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sw1_4:inst26\|temp\[15\]~545 " "Info: Destination \"sw1_4:inst26\|temp\[15\]~545\" may be non-global or may not use global clock" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sw1_4:inst23\|cnt " "Info: Destination \"sw1_4:inst23\|cnt\" may be non-global or may not use global clock" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 19 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sw1_4:inst23\|temp\[15\]~545 " "Info: Destination \"sw1_4:inst23\|temp\[15\]~545\" may be non-global or may not use global clock" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "oesel.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd" 11 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" {  } {  } 1 0 "Start inferring scan chains for DSP blocks" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" {  } {  } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0}