rader_hilbert_syn_hier_info

FPGA开发光盘各章节实例的设计工程与源码

clk => rd_contr:inst10|inst12.CLK
clk => rd_contr:inst10|inst3.CLK
clk => rd_contr:inst10|inst.CLK
clk => oesel:inst1|hlmux1.CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[6].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[5].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[4].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[3].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[2].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[1].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[0].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[15].CLK
clk => contrIQ:inst4|inst29.CLK
clk => rd_contract:inst22|conclk1.CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[14].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[13].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[12].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[11].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[10].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[9].CLK
clk => rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[8].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[6].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[5].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[4].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[3].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[2].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[1].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cs_buffer[0].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[15].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[14].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[13].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[12].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[11].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[10].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[9].CLK
clk => rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cs_buffer[8].CLK
clk => rd_contr:inst10|inst9.CLK
clk => expand:inst6|expout[31]~reg0.CLK
clk => contrIQ:inst4|inst26.CLK
clk => expand:inst17|expout[31]~reg0.CLK
clk => contrIQ:inst4|inst9.CLK
clk => expand:inst6|expout[6]~reg0.CLK
clk => expand:inst17|expout[6]~reg0.CLK
clk => expand:inst6|expout[5]~reg0.CLK
clk => expand:inst17|expout[5]~reg0.CLK
clk => expand:inst6|expout[4]~reg0.CLK
clk => expand:inst17|expout[4]~reg0.CLK
clk => expand:inst6|expout[3]~reg0.CLK
clk => expand:inst17|expout[3]~reg0.CLK
clk => expand:inst6|expout[2]~reg0.CLK
clk => expand:inst17|expout[2]~reg0.CLK
clk => expand:inst6|expout[1]~reg0.CLK
clk => expand:inst17|expout[1]~reg0.CLK
clk => expand:inst6|expout[0]~reg0.CLK
clk => expand:inst17|expout[0]~reg0.CLK
ad_end => rd_contr:inst10|inst.DATAA
xn[15] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[15].DATAA
xn[15] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[15].DATAA
xn[1] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[1].DATAA
xn[1] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[1].DATAA
xn[2] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[2].DATAA
xn[2] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2].DATAA
xn[3] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[3].DATAA
xn[3] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[3].DATAA
xn[4] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[4].DATAA
xn[4] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[4].DATAA
xn[5] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[5].DATAA
xn[5] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[5].DATAA
xn[6] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[6].DATAA
xn[6] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[6].DATAA
xn[7] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[7].DATAA
xn[7] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[7].DATAA
xn[8] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8].DATAA
xn[8] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[8].DATAA
xn[9] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[9].DATAA
xn[9] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[9].DATAA
xn[10] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[10].DATAA
xn[10] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[10].DATAA
xn[11] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[11].DATAA
xn[11] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[11].DATAA
xn[12] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[12].DATAA
xn[12] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[12].DATAA
xn[13] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[13].DATAA
xn[13] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[13].DATAA
xn[14] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[14].DATAA
xn[14] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[14].DATAA
xn[0] => indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0].DATAA
xn[0] => indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[0].DATAA
adenddly6 <= rd_contr:inst10|inst23
In[15] <= sw1_4:inst26|outdata[15]~reg0
In[14] <= sw1_4:inst26|outdata[14]~reg0
In[13] <= sw1_4:inst26|outdata[13]~reg0
In[12] <= sw1_4:inst26|outdata[12]~reg0
In[11] <= sw1_4:inst26|outdata[11]~reg0
In[10] <= sw1_4:inst26|outdata[10]~reg0
In[9] <= sw1_4:inst26|outdata[9]~reg0
In[8] <= sw1_4:inst26|outdata[8]~reg0
In[7] <= sw1_4:inst26|outdata[7]~reg0
In[6] <= sw1_4:inst26|outdata[6]~reg0
In[5] <= sw1_4:inst26|outdata[5]~reg0
In[4] <= sw1_4:inst26|outdata[4]~reg0
In[3] <= sw1_4:inst26|outdata[3]~reg0
In[2] <= sw1_4:inst26|outdata[2]~reg0
In[1] <= sw1_4:inst26|outdata[1]~reg0
In[0] <= sw1_4:inst26|outdata[0]~reg0
Qn[15] <= sw1_4:inst23|outdata[15]~reg0
Qn[14] <= sw1_4:inst23|outdata[14]~reg0
Qn[13] <= sw1_4:inst23|outdata[13]~reg0
Qn[12] <= sw1_4:inst23|outdata[12]~reg0
Qn[11] <= sw1_4:inst23|outdata[11]~reg0
Qn[10] <= sw1_4:inst23|outdata[10]~reg0
Qn[9] <= sw1_4:inst23|outdata[9]~reg0
Qn[8] <= sw1_4:inst23|outdata[8]~reg0
Qn[7] <= sw1_4:inst23|outdata[7]~reg0
Qn[6] <= sw1_4:inst23|outdata[6]~reg0
Qn[5] <= sw1_4:inst23|outdata[5]~reg0
Qn[4] <= sw1_4:inst23|outdata[4]~reg0
Qn[3] <= sw1_4:inst23|outdata[3]~reg0
Qn[2] <= sw1_4:inst23|outdata[2]~reg0
Qn[1] <= sw1_4:inst23|outdata[1]~reg0
Qn[0] <= sw1_4:inst23|outdata[0]~reg0