rader_hilbert.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk Qn\[7\] sw1_4:inst23\|outdata\[7\] 7.145 ns register " "Info: tco from clock \"clk\" to destination pin \"Qn\[7\]\" through register \"sw1_4:inst23\|outdata\[7\]\" is 7.145 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.972 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.602 ns) + CELL(0.542 ns) 2.972 ns sw1_4:inst23\|outdata\[7\] 2 REG LC_X66_Y6_N2 1 " "Info: 2: + IC(1.602 ns) + CELL(0.542 ns) = 2.972 ns; Loc. = LC_X66_Y6_N2; Fanout = 1; REG Node = 'sw1_4:inst23\|outdata\[7\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.144 ns" { clk sw1_4:inst23|outdata[7] } "NODE_NAME" } } { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.10 % ) " "Info: Total cell delay = 1.370 ns ( 46.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.602 ns ( 53.90 % ) " "Info: Total interconnect delay = 1.602 ns ( 53.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.972 ns" { clk sw1_4:inst23|outdata[7] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.972 ns" { clk clk~out0 sw1_4:inst23|outdata[7] } { 0.000ns 0.000ns 1.602ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.017 ns + Longest register pin " "Info: + Longest register to pin delay is 4.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sw1_4:inst23\|outdata\[7\] 1 REG LC_X66_Y6_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X66_Y6_N2; Fanout = 1; REG Node = 'sw1_4:inst23\|outdata\[7\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw1_4:inst23|outdata[7] } "NODE_NAME" } } { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(2.404 ns) 4.017 ns Qn\[7\] 2 PIN PIN_AG8 0 " "Info: 2: + IC(1.613 ns) + CELL(2.404 ns) = 4.017 ns; Loc. = PIN_AG8; Fanout = 0; PIN Node = 'Qn\[7\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { sw1_4:inst23|outdata[7] Qn[7] } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 704 1704 1880 720 "Qn\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 59.85 % ) " "Info: Total cell delay = 2.404 ns ( 59.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.613 ns ( 40.15 % ) " "Info: Total interconnect delay = 1.613 ns ( 40.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { sw1_4:inst23|outdata[7] Qn[7] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.017 ns" { sw1_4:inst23|outdata[7] Qn[7] } { 0.000ns 1.613ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.972 ns" { clk sw1_4:inst23|outdata[7] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.972 ns" { clk clk~out0 sw1_4:inst23|outdata[7] } { 0.000ns 0.000ns 1.602ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { sw1_4:inst23|outdata[7] Qn[7] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.017 ns" { sw1_4:inst23|outdata[7] Qn[7] } { 0.000ns 1.613ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "indatamux:inst\|rh_lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[8\] xn\[8\] clk 1.771 ns register " "Info: th for register \"indatamux:inst\|rh_lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[8\]\" (data pin = \"xn\[8\]\", clock pin = \"clk\") is 1.771 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.522 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(0.698 ns) 3.241 ns oesel:inst1\|evenen 2 REG LC_X1_Y25_N2 86 " "Info: 2: + IC(1.715 ns) + CELL(0.698 ns) = 3.241 ns; Loc. = LC_X1_Y25_N2; Fanout = 86; REG Node = 'oesel:inst1\|evenen'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.413 ns" { clk oesel:inst1|evenen } "NODE_NAME" } } { "oesel.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.739 ns) + CELL(0.542 ns) 6.522 ns indatamux:inst\|rh_lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[8\] 3 REG LC_X73_Y8_N2 4 " "Info: 3: + IC(2.739 ns) + CELL(0.542 ns) = 6.522 ns; Loc. = LC_X73_Y8_N2; Fanout = 4; REG Node = 'indatamux:inst\|rh_lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[8\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.281 ns" { oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 31.71 % ) " "Info: Total cell delay = 2.068 ns ( 31.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.454 ns ( 68.29 % ) " "Info: Total interconnect delay = 4.454 ns ( 68.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.522 ns" { clk oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.522 ns" { clk clk~out0 oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } { 0.000ns 0.000ns 1.715ns 2.739ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.851 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns xn\[8\] 1 PIN PIN_AC1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_AC1; Fanout = 2; PIN Node = 'xn\[8\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { xn[8] } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 440 -80 88 456 "xn\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.532 ns) + CELL(0.085 ns) 4.851 ns indatamux:inst\|rh_lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[8\] 2 REG LC_X73_Y8_N2 4 " "Info: 2: + IC(3.532 ns) + CELL(0.085 ns) = 4.851 ns; Loc. = LC_X73_Y8_N2; Fanout = 4; REG Node = 'indatamux:inst\|rh_lpm_dff0:inst\|lpm_ff:lpm_ff_component\|dffs\[8\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.617 ns" { xn[8] indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 27.19 % ) " "Info: Total cell delay = 1.319 ns ( 27.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.532 ns ( 72.81 % ) " "Info: Total interconnect delay = 3.532 ns ( 72.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.851 ns" { xn[8] indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.851 ns" { xn[8] xn[8]~out0 indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } { 0.000ns 0.000ns 3.532ns } { 0.000ns 1.234ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.522 ns" { clk oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.522 ns" { clk clk~out0 oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } { 0.000ns 0.000ns 1.715ns 2.739ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.851 ns" { xn[8] indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.851 ns" { xn[8] xn[8]~out0 indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8] } { 0.000ns 0.000ns 3.532ns } { 0.000ns 1.234ns 0.085ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk In\[6\] sw1_4:inst26\|outdata\[6\] 6.513 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"In\[6\]\" through register \"sw1_4:inst26\|outdata\[6\]\" is 6.513 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.999 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.629 ns) + CELL(0.542 ns) 2.999 ns sw1_4:inst26\|outdata\[6\] 2 REG LC_X76_Y15_N6 1 " "Info: 2: + IC(1.629 ns) + CELL(0.542 ns) = 2.999 ns; Loc. = LC_X76_Y15_N6; Fanout = 1; REG Node = 'sw1_4:inst26\|outdata\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.171 ns" { clk sw1_4:inst26|outdata[6] } "NODE_NAME" } } { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.68 % ) " "Info: Total cell delay = 1.370 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.629 ns ( 54.32 % ) " "Info: Total interconnect delay = 1.629 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk sw1_4:inst26|outdata[6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 sw1_4:inst26|outdata[6] } { 0.000ns 0.000ns 1.629ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.358 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sw1_4:inst26\|outdata\[6\] 1 REG LC_X76_Y15_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X76_Y15_N6; Fanout = 1; REG Node = 'sw1_4:inst26\|outdata\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw1_4:inst26|outdata[6] } "NODE_NAME" } } { "sw1_4.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(2.376 ns) 3.358 ns In\[6\] 2 PIN PIN_W3 0 " "Info: 2: + IC(0.982 ns) + CELL(2.376 ns) = 3.358 ns; Loc. = PIN_W3; Fanout = 0; PIN Node = 'In\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.358 ns" { sw1_4:inst26|outdata[6] In[6] } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 264 1704 1880 280 "In\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 70.76 % ) " "Info: Total cell delay = 2.376 ns ( 70.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 29.24 % ) " "Info: Total interconnect delay = 0.982 ns ( 29.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c: