rader_hilbert.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 32 " "Warning: Circuit may not operate. Detected 32 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "rd_contract:inst22\|wconout\[5\] rh_lpm_dff0:inst11\|lpm_ff:lpm_ff_component\|dffs\[5\] clk 3.032 ns " "Info: Found hold time violation between source  pin or register \"rd_contract:inst22\|wconout\[5\]\" and destination pin or register \"rh_lpm_dff0:inst11\|lpm_ff:lpm_ff_component\|dffs\[5\]\" for clock \"clk\" (Hold time is 3.032 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.575 ns + Largest " "Info: + Largest clock skew is 3.575 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.574 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(0.698 ns) 3.241 ns oesel:inst1\|evenen 2 REG LC_X1_Y25_N2 86 " "Info: 2: + IC(1.715 ns) + CELL(0.698 ns) = 3.241 ns; Loc. = LC_X1_Y25_N2; Fanout = 86; REG Node = 'oesel:inst1\|evenen'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.413 ns" { clk oesel:inst1|evenen } "NODE_NAME" } } { "oesel.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.791 ns) + CELL(0.542 ns) 6.574 ns rh_lpm_dff0:inst11\|lpm_ff:lpm_ff_component\|dffs\[5\] 3 REG LC_X72_Y15_N2 3 " "Info: 3: + IC(2.791 ns) + CELL(0.542 ns) = 6.574 ns; Loc. = LC_X72_Y15_N2; Fanout = 3; REG Node = 'rh_lpm_dff0:inst11\|lpm_ff:lpm_ff_component\|dffs\[5\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.333 ns" { oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 31.46 % ) " "Info: Total cell delay = 2.068 ns ( 31.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.506 ns ( 68.54 % ) " "Info: Total interconnect delay = 4.506 ns ( 68.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.574 ns" { clk oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.574 ns" { clk clk~out0 oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } { 0.000ns 0.000ns 1.715ns 2.791ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.999 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.629 ns) + CELL(0.542 ns) 2.999 ns rd_contract:inst22\|wconout\[5\] 2 REG LC_X72_Y15_N3 2 " "Info: 2: + IC(1.629 ns) + CELL(0.542 ns) = 2.999 ns; Loc. = LC_X72_Y15_N3; Fanout = 2; REG Node = 'rd_contract:inst22\|wconout\[5\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.171 ns" { clk rd_contract:inst22|wconout[5] } "NODE_NAME" } } { "rd_contract.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contract.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.68 % ) " "Info: Total cell delay = 1.370 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.629 ns ( 54.32 % ) " "Info: Total interconnect delay = 1.629 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk rd_contract:inst22|wconout[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 rd_contract:inst22|wconout[5] } { 0.000ns 0.000ns 1.629ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.574 ns" { clk oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.574 ns" { clk clk~out0 oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } { 0.000ns 0.000ns 1.715ns 2.791ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk rd_contract:inst22|wconout[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 rd_contract:inst22|wconout[5] } { 0.000ns 0.000ns 1.629ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "rd_contract.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contract.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.487 ns - Shortest register register " "Info: - Shortest register to register delay is 0.487 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rd_contract:inst22\|wconout\[5\] 1 REG LC_X72_Y15_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X72_Y15_N3; Fanout = 2; REG Node = 'rd_contract:inst22\|wconout\[5\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_contract:inst22|wconout[5] } "NODE_NAME" } } { "rd_contract.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contract.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.085 ns) 0.487 ns rh_lpm_dff0:inst11\|lpm_ff:lpm_ff_component\|dffs\[5\] 2 REG LC_X72_Y15_N2 3 " "Info: 2: + IC(0.402 ns) + CELL(0.085 ns) = 0.487 ns; Loc. = LC_X72_Y15_N2; Fanout = 3; REG Node = 'rh_lpm_dff0:inst11\|lpm_ff:lpm_ff_component\|dffs\[5\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.487 ns" { rd_contract:inst22|wconout[5] rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.085 ns ( 17.45 % ) " "Info: Total cell delay = 0.085 ns ( 17.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.402 ns ( 82.55 % ) " "Info: Total interconnect delay = 0.402 ns ( 82.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.487 ns" { rd_contract:inst22|wconout[5] rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.487 ns" { rd_contract:inst22|wconout[5] rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } { 0.000ns 0.402ns } { 0.000ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.574 ns" { clk oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.574 ns" { clk clk~out0 oesel:inst1|evenen rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } { 0.000ns 0.000ns 1.715ns 2.791ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk rd_contract:inst22|wconout[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk clk~out0 rd_contract:inst22|wconout[5] } { 0.000ns 0.000ns 1.629ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.487 ns" { rd_contract:inst22|wconout[5] rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.487 ns" { rd_contract:inst22|wconout[5] rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5] } { 0.000ns 0.402ns } { 0.000ns 0.085ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "rd_contr:inst10\|inst ad_end clk 1.407 ns register " "Info: tsu for register \"rd_contr:inst10\|inst\" (data pin = \"ad_end\", clock pin = \"clk\") is 1.407 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.482 ns + Longest pin register " "Info: + Longest pin to register delay is 4.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns ad_end 1 PIN PIN_P27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_P27; Fanout = 1; PIN Node = 'ad_end'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad_end } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 496 -80 88 512 "ad_end" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.672 ns) + CELL(0.085 ns) 4.482 ns rd_contr:inst10\|inst 2 REG LC_X1_Y25_N5 3 " "Info: 2: + IC(3.672 ns) + CELL(0.085 ns) = 4.482 ns; Loc. = LC_X1_Y25_N5; Fanout = 3; REG Node = 'rd_contr:inst10\|inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.757 ns" { ad_end rd_contr:inst10|inst } "NODE_NAME" } } { "rd_contr.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contr.bdf" { { 72 128 192 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.810 ns ( 18.07 % ) " "Info: Total cell delay = 0.810 ns ( 18.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.672 ns ( 81.93 % ) " "Info: Total interconnect delay = 3.672 ns ( 81.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { ad_end rd_contr:inst10|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.482 ns" { ad_end ad_end~out0 rd_contr:inst10|inst } { 0.000ns 0.000ns 3.672ns } { 0.000ns 0.725ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "rd_contr.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contr.bdf" { { 72 128 192 152 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.085 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(0.542 ns) 3.085 ns rd_contr:inst10\|inst 2 REG LC_X1_Y25_N5 3 " "Info: 2: + IC(1.715 ns) + CELL(0.542 ns) = 3.085 ns; Loc. = LC_X1_Y25_N5; Fanout = 3; REG Node = 'rd_contr:inst10\|inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.257 ns" { clk rd_contr:inst10|inst } "NODE_NAME" } } { "rd_contr.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contr.bdf" { { 72 128 192 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.41 % ) " "Info: Total cell delay = 1.370 ns ( 44.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.715 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.715 ns ( 55.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.085 ns" { clk rd_contr:inst10|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.085 ns" { clk clk~out0 rd_contr:inst10|inst } { 0.000ns 0.000ns 1.715ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { ad_end rd_contr:inst10|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.482 ns" { ad_end ad_end~out0 rd_contr:inst10|inst } { 0.000ns 0.000ns 3.672ns } { 0.000ns 0.725ns 0.085ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.085 ns" { clk rd_contr:inst10|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.085 ns" { clk clk~out0 rd_contr:inst10|inst } { 0.000ns 0.000ns 1.715ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}