rader_hilbert.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "oesel:inst1\|evenen " "Info: Detected ripple clock \"oesel:inst1\|evenen\" as buffer" {  } { { "oesel.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd" 11 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "oesel:inst1\|evenen" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register indatamux:inst\|rh_lpm_dff0:inst1\|lpm_ff:lpm_ff_component\|dffs\[2\] register rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[15\] 38.35 MHz 26.074 ns Internal " "Info: Clock \"clk\" has Internal fmax of 38.35 MHz between source register \"indatamux:inst\|rh_lpm_dff0:inst1\|lpm_ff:lpm_ff_component\|dffs\[2\]\" and destination register \"rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[15\]\" (period= 26.074 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.325 ns + Longest register register " "Info: + Longest register to register delay is 9.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns indatamux:inst\|rh_lpm_dff0:inst1\|lpm_ff:lpm_ff_component\|dffs\[2\] 1 REG LC_X71_Y9_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X71_Y9_N9; Fanout = 2; REG Node = 'indatamux:inst\|rh_lpm_dff0:inst1\|lpm_ff:lpm_ff_component\|dffs\[2\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.524 ns) 1.346 ns adddiv2:inst44\|rd_lpm_add_sub0:lpm_add_sub0_component\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~306 2 COMB LC_X67_Y9_N4 6 " "Info: 2: + IC(0.822 ns) + CELL(0.524 ns) = 1.346 ns; Loc. = LC_X67_Y9_N4; Fanout = 6; COMB Node = 'adddiv2:inst44\|rd_lpm_add_sub0:lpm_add_sub0_component\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~306'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.346 ns" { indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~306 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 1.795 ns adddiv2:inst44\|rd_lpm_add_sub0:lpm_add_sub0_component\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~307 3 COMB LC_X67_Y9_N5 32 " "Info: 3: + IC(0.000 ns) + CELL(0.449 ns) = 1.795 ns; Loc. = LC_X67_Y9_N5; Fanout = 32; COMB Node = 'adddiv2:inst44\|rd_lpm_add_sub0:lpm_add_sub0_component\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~307'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~306 adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(3.451 ns) 6.315 ns rh_lpm_mult_Q:inst2\|lpm_mult:lpm_mult_component\|mult_v7u:auto_generated\|mac_mult2~DATAOUT31 4 COMB DSPMULT_X68_Y7_N0 24 " "Info: 4: + IC(1.069 ns) + CELL(3.451 ns) = 6.315 ns; Loc. = DSPMULT_X68_Y7_N0; Fanout = 24; COMB Node = 'rh_lpm_mult_Q:inst2\|lpm_mult:lpm_mult_component\|mult_v7u:auto_generated\|mac_mult2~DATAOUT31'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.520 ns" { adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31 } "NODE_NAME" } } { "db/mult_v7u.tdf" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/db/mult_v7u.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 7.193 ns rh_lpm_mult_Q:inst2\|lpm_mult:lpm_mult_component\|mult_v7u:auto_generated\|result\[8\] 5 COMB DSPOUT_X69_Y1_N0 3 " "Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 7.193 ns; Loc. = DSPOUT_X69_Y1_N0; Fanout = 3; COMB Node = 'rh_lpm_mult_Q:inst2\|lpm_mult:lpm_mult_component\|mult_v7u:auto_generated\|result\[8\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[8] } "NODE_NAME" } } { "db/mult_v7u.tdf" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/db/mult_v7u.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.344 ns) 8.443 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[8\]~92 6 COMB LC_X70_Y7_N0 2 " "Info: 6: + IC(0.906 ns) + CELL(0.344 ns) = 8.443 ns; Loc. = LC_X70_Y7_N0; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[8\]~92'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[8] rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~92 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 8.501 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[9\]~91 7 COMB LC_X70_Y7_N1 2 " "Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 8.501 ns; Loc. = LC_X70_Y7_N1; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[9\]~91'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~92 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~91 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 8.559 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]~90 8 COMB LC_X70_Y7_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.058 ns) = 8.559 ns; Loc. = LC_X70_Y7_N2; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[10\]~90'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~91 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~90 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 8.617 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[11\]~89 9 COMB LC_X70_Y7_N3 2 " "Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 8.617 ns; Loc. = LC_X70_Y7_N3; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[11\]~89'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~90 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~89 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 8.747 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]~88 10 COMB LC_X70_Y7_N4 4 " "Info: 10: + IC(0.000 ns) + CELL(0.130 ns) = 8.747 ns; Loc. = LC_X70_Y7_N4; Fanout = 4; COMB Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]~88'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.130 ns" { rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~89 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~88 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 9.325 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[15\] 11 REG LC_X70_Y7_N7 1 " "Info: 11: + IC(0.000 ns) + CELL(0.578 ns) = 9.325 ns; Loc. = LC_X70_Y7_N7; Fanout = 1; REG Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[15\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.578 ns" { rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~88 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.528 ns ( 70.01 % ) " "Info: Total cell delay = 6.528 ns ( 70.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.797 ns ( 29.99 % ) " "Info: Total interconnect delay = 2.797 ns ( 29.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.325 ns" { indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~306 adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[8] rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~92 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~91 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~90 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~89 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~88 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.325 ns" { indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~306 adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[8] rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~92 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~91 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~90 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~89 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~88 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } { 0.000ns 0.822ns 0.000ns 1.069ns 0.000ns 0.906ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.524ns 0.449ns 3.451ns 0.878ns 0.344ns 0.058ns 0.058ns 0.058ns 0.130ns 0.578ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.546 ns - Smallest " "Info: - Smallest clock skew is -3.546 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.964 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.594 ns) + CELL(0.542 ns) 2.964 ns rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[15\] 2 REG LC_X70_Y7_N7 1 " "Info: 2: + IC(1.594 ns) + CELL(0.542 ns) = 2.964 ns; Loc. = LC_X70_Y7_N7; Fanout = 1; REG Node = 'rh_lpm_add_sub1:inst21\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[15\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.136 ns" { clk rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.22 % ) " "Info: Total cell delay = 1.370 ns ( 46.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.594 ns ( 53.78 % ) " "Info: Total interconnect delay = 1.594 ns ( 53.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.964 ns" { clk rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.964 ns" { clk clk~out0 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } { 0.000ns 0.000ns 1.594ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.510 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 162 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 162; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "rader_hilbert.bdf" "" { Schematic "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf" { { 568 -80 88 584 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(0.698 ns) 3.241 ns oesel:inst1\|evenen 2 REG LC_X1_Y25_N2 86 " "Info: 2: + IC(1.715 ns) + CELL(0.698 ns) = 3.241 ns; Loc. = LC_X1_Y25_N2; Fanout = 86; REG Node = 'oesel:inst1\|evenen'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.413 ns" { clk oesel:inst1|evenen } "NODE_NAME" } } { "oesel.vhd" "" { Text "F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.727 ns) + CELL(0.542 ns) 6.510 ns indatamux:inst\|rh_lpm_dff0:inst1\|lpm_ff:lpm_ff_component\|dffs\[2\] 3 REG LC_X71_Y9_N9 2 " "Info: 3: + IC(2.727 ns) + CELL(0.542 ns) = 6.510 ns; Loc. = LC_X71_Y9_N9; Fanout = 2; REG Node = 'indatamux:inst\|rh_lpm_dff0:inst1\|lpm_ff:lpm_ff_component\|dffs\[2\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.269 ns" { oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 31.77 % ) " "Info: Total cell delay = 2.068 ns ( 31.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.442 ns ( 68.23 % ) " "Info: Total interconnect delay = 4.442 ns ( 68.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.510 ns" { clk oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.510 ns" { clk clk~out0 oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } { 0.000ns 0.000ns 1.715ns 2.727ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.964 ns" { clk rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.964 ns" { clk clk~out0 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } { 0.000ns 0.000ns 1.594ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.510 ns" { clk oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.510 ns" { clk clk~out0 oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } { 0.000ns 0.000ns 1.715ns 2.727ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } } { "a_csnbuffer.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.325 ns" { indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~306 adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[8] rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~92 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~91 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~90 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~89 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~88 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.325 ns" { indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~306 adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~307 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31 rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[8] rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~92 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~91 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~90 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~89 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~88 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } { 0.000ns 0.822ns 0.000ns 1.069ns 0.000ns 0.906ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.524ns 0.449ns 3.451ns 0.878ns 0.344ns 0.058ns 0.058ns 0.058ns 0.130ns 0.578ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.964 ns" { clk rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.964 ns" { clk clk~out0 rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] } { 0.000ns 0.000ns 1.594ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.510 ns" { clk oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.510 ns" { clk clk~out0 oesel:inst1|evenen indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] } { 0.000ns 0.000ns 1.715ns 2.727ns } { 0.000ns 0.828ns 0.698ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}