rd_contract.vhd

FPGA开发光盘各章节实例的设计工程与源码

LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity rd_contract is 
  port(
	clk									   : in  std_logic;
	conin                                  : in  std_logic_vector(31 downto 0);
	conclk						  	       : in  std_logic;
	wconout								   : out std_logic_vector(15 downto 0)	
		);
end rd_contract;
architecture behv of rd_contract is
	signal 		conclk1		: std_logic;
begin
process (clk)
  begin	
	if (clk'event and clk='1') then
		conclk1<=conclk;
	  if ((not conclk1) and conclk)='1' then 
	            wconout<=conin(23 downto 8);		
	  end if;
	end if;-- end of clk'event;
end process;
end behv;