sw1_4.inc

FPGA开发光盘各章节实例的设计工程与源码

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2002 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
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-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
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-- Generated by Quartus II Version 2.1 (Build Build 189 09/05/2002)
-- Created on Mon Jun 16 23:31:55 2003

FUNCTION sw1_4 (clk, ad_clk, indata[7..0])
	RETURNS (outdata[7..0]);