rader_hilbert.fit.eqn

FPGA开发光盘各章节实例的设计工程与源码

--operation mode is arithmetic

L2L22Q_lut_out = X81_sout_node[4] $ !L2L02;
L2L22Q = DFFEA(L2L22Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--X51_cout[4] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4] at LC_X66_Y7_N4
--operation mode is arithmetic

X51_cout[4] = L2L32;


--L2L91Q is rd_contract:inst25|wconout[11]~reg0 at LC_X66_Y7_N3
--operation mode is arithmetic

L2L91Q_lut_out = X81_sout_node[3] $ L2L71;
L2L91Q = DFFEA(L2L91Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--L2L02 is rd_contract:inst25|wconout[11]~reg0COUT0 at LC_X66_Y7_N3
--operation mode is arithmetic

L2L02_cout_0 = !L2L71 # !X81_sout_node[3];
L2L02 = CARRY(L2L02_cout_0);

--L2L12 is rd_contract:inst25|wconout[11]~reg0COUT1 at LC_X66_Y7_N3
--operation mode is arithmetic

L2L12_cout_1 = !L2L81 # !X81_sout_node[3];
L2L12 = CARRY(L2L12_cout_1);


--L2L61Q is rd_contract:inst25|wconout[10]~reg0 at LC_X66_Y7_N2
--operation mode is arithmetic

L2L61Q_lut_out = X81_sout_node[2] $ !L2L41;
L2L61Q = DFFEA(L2L61Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--L2L71 is rd_contract:inst25|wconout[10]~reg0COUT0 at LC_X66_Y7_N2
--operation mode is arithmetic

L2L71_cout_0 = X81_sout_node[2] & !L2L41;
L2L71 = CARRY(L2L71_cout_0);

--L2L81 is rd_contract:inst25|wconout[10]~reg0COUT1 at LC_X66_Y7_N2
--operation mode is arithmetic

L2L81_cout_1 = X81_sout_node[2] & !L2L51;
L2L81 = CARRY(L2L81_cout_1);


--L2L31Q is rd_contract:inst25|wconout[9]~reg0 at LC_X66_Y7_N1
--operation mode is arithmetic

L2L31Q_lut_out = X81_sout_node[1] $ L2L11;
L2L31Q = DFFEA(L2L31Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--L2L41 is rd_contract:inst25|wconout[9]~reg0COUT0 at LC_X66_Y7_N1
--operation mode is arithmetic

L2L41_cout_0 = !L2L11 # !X81_sout_node[1];
L2L41 = CARRY(L2L41_cout_0);

--L2L51 is rd_contract:inst25|wconout[9]~reg0COUT1 at LC_X66_Y7_N1
--operation mode is arithmetic

L2L51_cout_1 = !L2L21 # !X81_sout_node[1];
L2L51 = CARRY(L2L51_cout_1);


--L2L01Q is rd_contract:inst25|wconout[8]~reg0 at LC_X66_Y7_N0
--operation mode is arithmetic

L2L01Q_lut_out = X21_sout_node[16] $ X81_sout_node[0];
L2L01Q = DFFEA(L2L01Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--L2L11 is rd_contract:inst25|wconout[8]~reg0COUT0 at LC_X66_Y7_N0
--operation mode is arithmetic

L2L11_cout_0 = X21_sout_node[16] & X81_sout_node[0];
L2L11 = CARRY(L2L11_cout_0);

--L2L21 is rd_contract:inst25|wconout[8]~reg0COUT1 at LC_X66_Y7_N0
--operation mode is arithmetic

L2L21_cout_1 = X21_sout_node[16] & X81_sout_node[0];
L2L21 = CARRY(L2L21_cout_1);


--L2L9Q is rd_contract:inst25|wconout[7]~reg0 at LC_X70_Y7_N9
--operation mode is normal

L2L9Q_sload_eqn = X21_sout_node[15];
L2L9Q = DFFEA(L2L9Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L8Q is rd_contract:inst25|wconout[6]~reg0 at LC_X66_Y8_N3
--operation mode is normal

L2L8Q_sload_eqn = X21_sout_node[14];
L2L8Q = DFFEA(L2L8Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L7Q is rd_contract:inst25|wconout[5]~reg0 at LC_X70_Y9_N6
--operation mode is normal

L2L7Q_sload_eqn = X21_sout_node[13];
L2L7Q = DFFEA(L2L7Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L6Q is rd_contract:inst25|wconout[4]~reg0 at LC_X70_Y9_N5
--operation mode is normal

L2L6Q_sload_eqn = X21_sout_node[12];
L2L6Q = DFFEA(L2L6Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L5Q is rd_contract:inst25|wconout[3]~reg0 at LC_X70_Y9_N4
--operation mode is normal

L2L5Q_sload_eqn = X21_sout_node[11];
L2L5Q = DFFEA(L2L5Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L4Q is rd_contract:inst25|wconout[2]~reg0 at LC_X70_Y9_N9
--operation mode is normal

L2L4Q_sload_eqn = X21_sout_node[10];
L2L4Q = DFFEA(L2L4Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L3Q is rd_contract:inst25|wconout[1]~reg0 at LC_X66_Y7_N9
--operation mode is normal

L2L3Q_sload_eqn = X21_sout_node[9];
L2L3Q = DFFEA(L2L3Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--L2L2Q is rd_contract:inst25|wconout[0]~reg0 at LC_X70_Y9_N2
--operation mode is normal

L2L2Q_sload_eqn = X21_sout_node[8];
L2L2Q = DFFEA(L2L2Q_sload_eqn, GLOBAL(clk), VCC, , L2L1, , );


--G1_inst12 is rd_contr:inst10|inst12 at LC_X1_Y25_N1
--operation mode is normal

G1_inst12_lut_out = G1_inst9;
G1_inst12 = DFFEA(G1_inst12_lut_out, GLOBAL(clk), VCC, , , , );


--G1_inst is rd_contr:inst10|inst at LC_X1_Y25_N7
--operation mode is normal

G1_inst_sload_eqn = ad_end;
G1_inst = DFFEA(G1_inst_sload_eqn, GLOBAL(clk), VCC, , , , );


--C1_hlmux1 is oesel:inst1|hlmux1 at LC_X1_Y25_N8
--operation mode is normal

C1_hlmux1_lut_out = !G1_inst & G1_inst3;
C1_hlmux1 = DFFEA(C1_hlmux1_lut_out, GLOBAL(clk), VCC, , , , );


--C1L2 is oesel:inst1|i~0 at LC_X1_Y25_N9
--operation mode is normal

G1_inst3_qfbk = G1_inst3;
C1L2 = !G1_inst & G1_inst3_qfbk & !C1_hlmux1;

--G1_inst3 is rd_contr:inst10|inst3 at LC_X1_Y25_N9
--operation mode is normal

G1_inst3_sload_eqn = G1_inst;
G1_inst3 = DFFEA(G1_inst3_sload_eqn, GLOBAL(clk), VCC, , , , );


--M2L3 is sw1_4:inst26|i~0 at LC_X67_Y17_N5
--operation mode is normal

M2L3 = C1L3Q & !M2_ad_clk1;


--X9_sout_node[6] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6] at LC_X70_Y23_N6
--operation mode is arithmetic

X9_sout_node[6]_carry_eqn = (!X9_cout[4] & X9L62) # (X9_cout[4] & X9L72);
X9_sout_node[6]_lut_out = F1L8Q $ S2_result[22] $ !X9_sout_node[6]_carry_eqn;
X9_sout_node[6] = DFFEA(X9_sout_node[6]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9L92 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~COUT0 at LC_X70_Y23_N6
--operation mode is arithmetic

X9L92_cout_0 = F1L8Q & (S2_result[22] # !X9L62) # !F1L8Q & S2_result[22] & !X9L62;
X9L92 = CARRY(X9L92_cout_0);

--X9L03 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~COUT1 at LC_X70_Y23_N6
--operation mode is arithmetic

X9L03_cout_1 = F1L8Q & (S2_result[22] # !X9L72) # !F1L8Q & S2_result[22] & !X9L72;
X9L03 = CARRY(X9L03_cout_1);


--X9_sout_node[5] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] at LC_X70_Y23_N5
--operation mode is arithmetic

X9_sout_node[5]_carry_eqn = (!X9_cout[4] & GND) # (X9_cout[4] & VCC);
X9_sout_node[5]_lut_out = F1L8Q $ S2_result[21] $ X9_sout_node[5]_carry_eqn;
X9_sout_node[5] = DFFEA(X9_sout_node[5]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9L62 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~COUT0 at LC_X70_Y23_N5
--operation mode is arithmetic

X9L62_cout_0 = F1L8Q & !S2_result[21] & !X9_cout[4] # !F1L8Q & (!X9_cout[4] # !S2_result[21]);
X9L62 = CARRY(X9L62_cout_0);

--X9L72 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~COUT1 at LC_X70_Y23_N5
--operation mode is arithmetic

X9L72_cout_1 = F1L8Q & !S2_result[21] & !X9_cout[4] # !F1L8Q & (!X9_cout[4] # !S2_result[21]);
X9L72 = CARRY(X9L72_cout_1);


--X9_sout_node[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] at LC_X70_Y23_N4
--operation mode is arithmetic

X9_sout_node[4]_lut_out = S2_result[20] $ F1L8Q $ !X9L02;
X9_sout_node[4] = DFFEA(X9_sout_node[4]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[4] at LC_X70_Y23_N4
--operation mode is arithmetic

X9_cout[4] = X9L32;


--X9_sout_node[3] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] at LC_X70_Y23_N3
--operation mode is arithmetic

X9_sout_node[3]_lut_out = F1L8Q $ S2_result[19] $ X9L71;
X9_sout_node[3] = DFFEA(X9_sout_node[3]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9L02 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~COUT0 at LC_X70_Y23_N3
--operation mode is arithmetic

X9L02_cout_0 = F1L8Q & !S2_result[19] & !X9L71 # !F1L8Q & (!X9L71 # !S2_result[19]);
X9L02 = CARRY(X9L02_cout_0);

--X9L12 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~COUT1 at LC_X70_Y23_N3
--operation mode is arithmetic

X9L12_cout_1 = F1L8Q & !S2_result[19] & !X9L81 # !F1L8Q & (!X9L81 # !S2_result[19]);
X9L12 = CARRY(X9L12_cout_1);


--X9_sout_node[2] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2] at LC_X70_Y23_N2
--operation mode is arithmetic

X9_sout_node[2]_lut_out = F1L8Q $ S2_result[18] $ !X9L41;
X9_sout_node[2] = DFFEA(X9_sout_node[2]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9L71 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~COUT0 at LC_X70_Y23_N2
--operation mode is arithmetic

X9L71_cout_0 = F1L8Q & (S2_result[18] # !X9L41) # !F1L8Q & S2_result[18] & !X9L41;
X9L71 = CARRY(X9L71_cout_0);

--X9L81 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~COUT1 at LC_X70_Y23_N2
--operation mode is arithmetic

X9L81_cout_1 = F1L8Q & (S2_result[18] # !X9L51) # !F1L8Q & S2_result[18] & !X9L51;
X9L81 = CARRY(X9L81_cout_1);


--X9_sout_node[1] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1] at LC_X70_Y23_N1
--operation mode is arithmetic

X9_sout_node[1]_lut_out = F1L8Q $ S2_result[17] $ X9L11;
X9_sout_node[1] = DFFEA(X9_sout_node[1]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9L41 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~COUT0 at LC_X70_Y23_N1
--operation mode is arithmetic

X9L41_cout_0 = F1L8Q & !S2_result[17] & !X9L11 # !F1L8Q & (!X9L11 # !S2_result[17]);
X9L41 = CARRY(X9L41_cout_0);

--X9L51 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~COUT1 at LC_X70_Y23_N1
--operation mode is arithmetic

X9L51_cout_1 = F1L8Q & !S2_result[17] & !X9L21 # !F1L8Q & (!X9L21 # !S2_result[17]);
X9L51 = CARRY(X9L51_cout_1);


--X9_sout_node[0] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] at LC_X70_Y23_N0
--operation mode is arithmetic

X9_sout_node[0]_lut_out = F1L8Q $ S2_result[16];
X9_sout_node[0] = DFFEA(X9_sout_node[0]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X9L11 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~COUT0 at LC_X70_Y23_N0
--operation mode is arithmetic

X9L11_cout_0 = F1L8Q & S2_result[16];
X9L11 = CARRY(X9L11_cout_0);

--X9L21 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~COUT1 at LC_X70_Y23_N0
--operation mode is arithmetic

X9L21_cout_1 = F1L8Q & S2_result[16];
X9L21 = CARRY(X9L21_cout_1);


--X3_sout_node[15] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] at LC_X70_Y24_N7
--operation mode is arithmetic

X3_sout_node[15]_carry_eqn = (!X3_cout[12] & X3L65) # (X3_cout[12] & X3L75);
X3_sout_node[15]_lut_out = F1L8Q $ S2_result[15] $ X3_sout_node[15]_carry_eqn;
X3_sout_node[15] = DFFEA(X3_sout_node[15]_lut_out, GLOBAL(clk), VCC, , E1_inst9, , );

--X3L95 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]~COUT0 at LC_X70_Y24_N7
--operation mode is arithmetic

X3L95_cout_0 = F1L8Q & !S2_result[15] & !X3L65 # !F1L8Q & (!X3L65 # !S2_result[15]);
X3L95 = CARRY(X3L95_cout_0);

--X3L06 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]~COUT1 at LC_X70_Y24_N7
--operation mode is arithmetic

X3L06_cout_1 = F1L8Q & !S2_result[15] & !X3L75 # !F1L8Q & (!X3L75 # !S2_result[15]);
X3L06 = CARRY(X3L06_cout_1);


--L1L2 is rd_contract:inst22|i~0 at LC_X71_Y22_N4
--operation mode is normal

E1_inst29_qfbk = E1_inst29;
L1L2 = E1_inst29_qfbk & !L1_conclk1;

--E1_inst29 is contrIQ:inst4|inst29 at LC_X71_Y22_N4
--operation mode is normal

E1_inst29_sload_eqn = E1_inst26;
E1_inst29 = DFFEA(E1_inst29_sload_eqn, GLOBAL(clk), VCC, , , , );


--X3_sout_node[14] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnb