rader_hilbert.fit.eqn

FPGA开发光盘各章节实例的设计工程与源码

M1_temp[10] = DFFEA(M1_temp[10]_lut_out, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[9] is sw1_4:inst23|temp[9] at LC_X65_Y8_N5
--operation mode is normal

M1_temp[9]_sload_eqn = L2L31Q;
M1_temp[9] = DFFEA(M1_temp[9]_sload_eqn, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[8] is sw1_4:inst23|temp[8] at LC_X66_Y7_N8
--operation mode is normal

M1_temp[8]_lut_out = L2L01Q;
M1_temp[8] = DFFEA(M1_temp[8]_lut_out, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[7] is sw1_4:inst23|temp[7] at LC_X65_Y7_N2
--operation mode is normal

M1_temp[7]_sload_eqn = L2L9Q;
M1_temp[7] = DFFEA(M1_temp[7]_sload_eqn, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[6] is sw1_4:inst23|temp[6] at LC_X66_Y10_N2
--operation mode is normal

M1_temp[6]_lut_out = L2L8Q;
M1_temp[6] = DFFEA(M1_temp[6]_lut_out, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[5] is sw1_4:inst23|temp[5] at LC_X66_Y10_N4
--operation mode is normal

M1_temp[5]_sload_eqn = L2L7Q;
M1_temp[5] = DFFEA(M1_temp[5]_sload_eqn, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[4] is sw1_4:inst23|temp[4] at LC_X67_Y17_N3
--operation mode is normal

M1_temp[4]_sload_eqn = L2L6Q;
M1_temp[4] = DFFEA(M1_temp[4]_sload_eqn, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[3] is sw1_4:inst23|temp[3] at LC_X67_Y17_N1
--operation mode is normal

M1_temp[3]_lut_out = L2L5Q;
M1_temp[3] = DFFEA(M1_temp[3]_lut_out, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[2] is sw1_4:inst23|temp[2] at LC_X67_Y17_N7
--operation mode is normal

M1_temp[2]_lut_out = L2L4Q;
M1_temp[2] = DFFEA(M1_temp[2]_lut_out, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[1] is sw1_4:inst23|temp[1] at LC_X67_Y6_N2
--operation mode is normal

M1_temp[1]_sload_eqn = L2L3Q;
M1_temp[1] = DFFEA(M1_temp[1]_sload_eqn, GLOBAL(clk), VCC, , M1L63, , );


--M1_temp[0] is sw1_4:inst23|temp[0] at LC_X67_Y6_N5
--operation mode is normal

M1_temp[0]_sload_eqn = L2L2Q;
M1_temp[0] = DFFEA(M1_temp[0]_sload_eqn, GLOBAL(clk), VCC, , M1L63, , );


--G1_inst17 is rd_contr:inst10|inst17 at LC_X1_Y25_N4
--operation mode is normal

G1_inst17_sload_eqn = G1_inst12;
G1_inst17 = DFFEA(G1_inst17_sload_eqn, GLOBAL(clk), VCC, , , , );


--C1L3Q is oesel:inst1|odden~reg0 at LC_X1_Y25_N5
--operation mode is normal

C1L3Q_lut_out = !C1L3Q;
C1L3Q = DFFEA(C1L3Q_lut_out, GLOBAL(clk), VCC, , C1L2, , );


--M2_cnt is sw1_4:inst26|cnt at LC_X66_Y17_N3
--operation mode is normal

M2_cnt_lut_out = !M2_cnt;
M2_cnt = DFFEA(M2_cnt_lut_out, GLOBAL(clk), VCC, , M2L3, , );


--M2L73 is sw1_4:inst26|temp[15]~0 at LC_X67_Y17_N2
--operation mode is normal

M2L73 = C1L3Q & !M2_cnt & !M2_ad_clk1;


--L1L92Q is rd_contract:inst22|wconout[14]~reg0 at LC_X71_Y23_N6
--operation mode is arithmetic

L1L92Q_carry_eqn = (!X6_cout[4] & L1L72) # (X6_cout[4] & L1L82);
L1L92Q_lut_out = X9_sout_node[6] $ !L1L92Q_carry_eqn;
L1L92Q = DFFEA(L1L92Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--L1L03 is rd_contract:inst22|wconout[14]~reg0COUT0 at LC_X71_Y23_N6
--operation mode is arithmetic

L1L03_cout_0 = X9_sout_node[6] & !L1L72;
L1L03 = CARRY(L1L03_cout_0);

--L1L13 is rd_contract:inst22|wconout[14]~reg0COUT1 at LC_X71_Y23_N6
--operation mode is arithmetic

L1L13_cout_1 = X9_sout_node[6] & !L1L82;
L1L13 = CARRY(L1L13_cout_1);


--L1L62Q is rd_contract:inst22|wconout[13]~reg0 at LC_X71_Y23_N5
--operation mode is arithmetic

L1L62Q_carry_eqn = (!X6_cout[4] & GND) # (X6_cout[4] & VCC);
L1L62Q_lut_out = X9_sout_node[5] $ L1L62Q_carry_eqn;
L1L62Q = DFFEA(L1L62Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--L1L72 is rd_contract:inst22|wconout[13]~reg0COUT0 at LC_X71_Y23_N5
--operation mode is arithmetic

L1L72_cout_0 = !X6_cout[4] # !X9_sout_node[5];
L1L72 = CARRY(L1L72_cout_0);

--L1L82 is rd_contract:inst22|wconout[13]~reg0COUT1 at LC_X71_Y23_N5
--operation mode is arithmetic

L1L82_cout_1 = !X6_cout[4] # !X9_sout_node[5];
L1L82 = CARRY(L1L82_cout_1);


--L1L32Q is rd_contract:inst22|wconout[12]~reg0 at LC_X71_Y23_N4
--operation mode is arithmetic

L1L32Q_lut_out = X9_sout_node[4] $ !L1L12;
L1L32Q = DFFEA(L1L32Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--X6_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4] at LC_X71_Y23_N4
--operation mode is arithmetic

X6_cout[4] = L1L42;


--L1L02Q is rd_contract:inst22|wconout[11]~reg0 at LC_X71_Y23_N3
--operation mode is arithmetic

L1L02Q_lut_out = X9_sout_node[3] $ L1L81;
L1L02Q = DFFEA(L1L02Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--L1L12 is rd_contract:inst22|wconout[11]~reg0COUT0 at LC_X71_Y23_N3
--operation mode is arithmetic

L1L12_cout_0 = !L1L81 # !X9_sout_node[3];
L1L12 = CARRY(L1L12_cout_0);

--L1L22 is rd_contract:inst22|wconout[11]~reg0COUT1 at LC_X71_Y23_N3
--operation mode is arithmetic

L1L22_cout_1 = !L1L91 # !X9_sout_node[3];
L1L22 = CARRY(L1L22_cout_1);


--L1L71Q is rd_contract:inst22|wconout[10]~reg0 at LC_X71_Y23_N2
--operation mode is arithmetic

L1L71Q_lut_out = X9_sout_node[2] $ !L1L51;
L1L71Q = DFFEA(L1L71Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--L1L81 is rd_contract:inst22|wconout[10]~reg0COUT0 at LC_X71_Y23_N2
--operation mode is arithmetic

L1L81_cout_0 = X9_sout_node[2] & !L1L51;
L1L81 = CARRY(L1L81_cout_0);

--L1L91 is rd_contract:inst22|wconout[10]~reg0COUT1 at LC_X71_Y23_N2
--operation mode is arithmetic

L1L91_cout_1 = X9_sout_node[2] & !L1L61;
L1L91 = CARRY(L1L91_cout_1);


--L1L41Q is rd_contract:inst22|wconout[9]~reg0 at LC_X71_Y23_N1
--operation mode is arithmetic

L1L41Q_lut_out = X9_sout_node[1] $ L1L21;
L1L41Q = DFFEA(L1L41Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--L1L51 is rd_contract:inst22|wconout[9]~reg0COUT0 at LC_X71_Y23_N1
--operation mode is arithmetic

L1L51_cout_0 = !L1L21 # !X9_sout_node[1];
L1L51 = CARRY(L1L51_cout_0);

--L1L61 is rd_contract:inst22|wconout[9]~reg0COUT1 at LC_X71_Y23_N1
--operation mode is arithmetic

L1L61_cout_1 = !L1L31 # !X9_sout_node[1];
L1L61 = CARRY(L1L61_cout_1);


--L1L11Q is rd_contract:inst22|wconout[8]~reg0 at LC_X71_Y23_N0
--operation mode is arithmetic

L1L11Q_lut_out = X9_sout_node[0] $ X3_sout_node[16];
L1L11Q = DFFEA(L1L11Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );

--L1L21 is rd_contract:inst22|wconout[8]~reg0COUT0 at LC_X71_Y23_N0
--operation mode is arithmetic

L1L21_cout_0 = X9_sout_node[0] & X3_sout_node[16];
L1L21 = CARRY(L1L21_cout_0);

--L1L31 is rd_contract:inst22|wconout[8]~reg0COUT1 at LC_X71_Y23_N0
--operation mode is arithmetic

L1L31_cout_1 = X9_sout_node[0] & X3_sout_node[16];
L1L31 = CARRY(L1L31_cout_1);


--L1L01Q is rd_contract:inst22|wconout[7]~reg0 at LC_X72_Y24_N6
--operation mode is normal

L1L01Q_sload_eqn = X3_sout_node[15];
L1L01Q = DFFEA(L1L01Q_sload_eqn, GLOBAL(clk), VCC, , L1L2, , );


--L1L9Q is rd_contract:inst22|wconout[6]~reg0 at LC_X71_Y24_N4
--operation mode is normal

L1L9Q_lut_out = X3_sout_node[14];
L1L9Q = DFFEA(L1L9Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );


--L1L8Q is rd_contract:inst22|wconout[5]~reg0 at LC_X71_Y24_N0
--operation mode is normal

L1L8Q_lut_out = X3_sout_node[13];
L1L8Q = DFFEA(L1L8Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );


--L1L7Q is rd_contract:inst22|wconout[4]~reg0 at LC_X71_Y24_N1
--operation mode is normal

L1L7Q_lut_out = X3_sout_node[12];
L1L7Q = DFFEA(L1L7Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );


--L1L6Q is rd_contract:inst22|wconout[3]~reg0 at LC_X71_Y24_N9
--operation mode is normal

L1L6Q_sload_eqn = X3_sout_node[11];
L1L6Q = DFFEA(L1L6Q_sload_eqn, GLOBAL(clk), VCC, , L1L2, , );


--L1L5Q is rd_contract:inst22|wconout[2]~reg0 at LC_X71_Y24_N7
--operation mode is normal

L1L5Q_lut_out = X3_sout_node[10];
L1L5Q = DFFEA(L1L5Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );


--L1L4Q is rd_contract:inst22|wconout[1]~reg0 at LC_X72_Y24_N4
--operation mode is normal

L1L4Q_sload_eqn = X3_sout_node[9];
L1L4Q = DFFEA(L1L4Q_sload_eqn, GLOBAL(clk), VCC, , L1L2, , );


--L1L3Q is rd_contract:inst22|wconout[0]~reg0 at LC_X71_Y24_N5
--operation mode is normal

L1L3Q_lut_out = X3_sout_node[8];
L1L3Q = DFFEA(L1L3Q_lut_out, GLOBAL(clk), VCC, , L1L2, , );


--M1_cnt is sw1_4:inst23|cnt at LC_X67_Y18_N2
--operation mode is normal

M1_cnt_lut_out = !M1_cnt;
M1_cnt = DFFEA(M1_cnt_lut_out, GLOBAL(clk), VCC, , M1L2, , );


--M1L63 is sw1_4:inst23|temp[15]~0 at LC_X67_Y17_N0
--operation mode is normal

M2_ad_clk1_qfbk = M2_ad_clk1;
M1L63 = !C1L3Q & M2_ad_clk1_qfbk & !M1_cnt;

--M2_ad_clk1 is sw1_4:inst26|ad_clk1 at LC_X67_Y17_N0
--operation mode is normal

M2_ad_clk1_sload_eqn = C1L3Q;
M2_ad_clk1 = DFFEA(M2_ad_clk1_sload_eqn, GLOBAL(clk), VCC, , , , );


--L2L82Q is rd_contract:inst25|wconout[14]~reg0 at LC_X66_Y7_N6
--operation mode is arithmetic

L2L82Q_carry_eqn = (!X51_cout[4] & L2L62) # (X51_cout[4] & L2L72);
L2L82Q_lut_out = X81_sout_node[6] $ !L2L82Q_carry_eqn;
L2L82Q = DFFEA(L2L82Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--L2L92 is rd_contract:inst25|wconout[14]~reg0COUT0 at LC_X66_Y7_N6
--operation mode is arithmetic

L2L92_cout_0 = X81_sout_node[6] & !L2L62;
L2L92 = CARRY(L2L92_cout_0);

--L2L03 is rd_contract:inst25|wconout[14]~reg0COUT1 at LC_X66_Y7_N6
--operation mode is arithmetic

L2L03_cout_1 = X81_sout_node[6] & !L2L72;
L2L03 = CARRY(L2L03_cout_1);


--L2L52Q is rd_contract:inst25|wconout[13]~reg0 at LC_X66_Y7_N5
--operation mode is arithmetic

L2L52Q_carry_eqn = (!X51_cout[4] & GND) # (X51_cout[4] & VCC);
L2L52Q_lut_out = X81_sout_node[5] $ L2L52Q_carry_eqn;
L2L52Q = DFFEA(L2L52Q_lut_out, GLOBAL(clk), VCC, , L2L1, , );

--L2L62 is rd_contract:inst25|wconout[13]~reg0COUT0 at LC_X66_Y7_N5
--operation mode is arithmetic

L2L62_cout_0 = !X51_cout[4] # !X81_sout_node[5];
L2L62 = CARRY(L2L62_cout_0);

--L2L72 is rd_contract:inst25|wconout[13]~reg0COUT1 at LC_X66_Y7_N5
--operation mode is arithmetic

L2L72_cout_1 = !X51_cout[4] # !X81_sout_node[5];
L2L72 = CARRY(L2L72_cout_1);


--L2L22Q is rd_contract:inst25|wconout[12]~reg0 at LC_X66_Y7_N4