expand.vhd

FPGA开发光盘各章节实例的设计工程与源码

LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity expand is 
  port(
    clk									   : in  std_logic;
	expin                                  : in  std_logic_vector(15  downto 0);
	expout								   : out std_logic_vector(31 downto 0)
		);
end expand;
architecture behv of expand is
begin
process(clk)
 begin
   if (clk'event and clk='1') then
	for i in 0 to 23 loop  --15
	  expout(31-i)<=expin(15);
	end loop;
	  expout(7 downto 0)<=expin(15 downto 8);
   end if;
end process;
end behv;