rader_hilbert.map.rpt

FPGA开发光盘各章节实例的设计工程与源码

; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto DSP Block Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; rd_contr.bdf                     ; yes             ; User Block Diagram/Schematic File  ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contr.bdf        ;
; contrIQ.bdf                      ; yes             ; User Block Diagram/Schematic File  ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/contrIQ.bdf         ;
; oesel.vhd                        ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/oesel.vhd           ;
; indatamux.bdf                    ; yes             ; User Block Diagram/Schematic File  ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/indatamux.bdf       ;
; rh_lpm_dff0.vhd                  ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rh_lpm_dff0.vhd     ;
; subdiv2.vhd                      ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/subdiv2.vhd         ;
; adddiv2.vhd                      ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/adddiv2.vhd         ;
; rh_lpm_add_sub1.vhd              ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rh_lpm_add_sub1.vhd ;
; rd_contract.vhd                  ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_contract.vhd     ;
; rh_lpm_mult0.vhd                 ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rh_lpm_mult0.vhd    ;
; expand.vhd                       ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/expand.vhd          ;
; sw1_4.vhd                        ; yes             ; User VHDL File                     ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/sw1_4.vhd           ;
; rader_hilbert.bdf                ; yes             ; User Block Diagram/Schematic File  ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rader_hilbert.bdf   ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf           ;
; addcore.inc                      ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/addcore.inc               ;
; look_add.inc                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/look_add.inc              ;
; bypassff.inc                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/bypassff.inc              ;
; altshift.inc                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/altshift.inc              ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.inc   ;
; alt_mercury_add_sub.inc          ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/alt_mercury_add_sub.inc   ;
; aglobal61.inc                    ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/aglobal61.inc             ;
; addcore.tdf                      ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/addcore.tdf               ;
; a_csnbuffer.inc                  ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.inc           ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/a_csnbuffer.tdf           ;
; bypassff.tdf                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/bypassff.tdf              ;
; altshift.tdf                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/altshift.tdf              ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/lpm_mult.tdf              ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.inc           ;
; multcore.inc                     ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/multcore.inc              ;
; db/mult_v7u.tdf                  ; yes             ; Auto-Generated Megafunction        ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/db/mult_v7u.tdf     ;
; rd_lpm_add_sub2.vhd              ; yes             ; Other                              ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_lpm_add_sub2.vhd ;
; lpm_ff.tdf                       ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/lpm_ff.tdf                ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; c:/altera/61/quartus/libraries/megafunctions/lpm_constant.inc          ;
; rh_lpm_mult_Q.vhd                ; yes             ; Other                              ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rh_lpm_mult_Q.vhd   ;
; rd_lpm_add_sub0.vhd              ; yes             ; Other                              ; F:/liu/我的硕士论文/hilbert/rader_hilbert3/quartus/rd_lpm_add_sub0.vhd ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 296   ;
;     -- Combinational with no register       ; 54    ;
;     -- Register only                        ; 184   ;
;     -- Combinational with a register        ; 58    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 1     ;
;     -- 3 input functions                    ; 80    ;
;     -- 2 input functions                    ; 25    ;
;     -- 1 input functions                    ; 6     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 204   ;
;     -- arithmetic mode                      ; 92    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 242   ;
; Total logic cells in carry chains           ; 100   ;
; I/O pins                                    ; 51    ;
; DSP block 9-bit elements                    ; 4     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 162   ;