rader_hilbert.map.rpt

FPGA开发光盘各章节实例的设计工程与源码

Analysis & Synthesis report for rader_hilbert
Mon Dec 10 15:25:30 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis DSP Block Usage Summary
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Parameter Settings for User Entity Instance: rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component
 12. Parameter Settings for User Entity Instance: rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component
 13. Parameter Settings for User Entity Instance: subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component
 14. Parameter Settings for User Entity Instance: rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component
 15. Parameter Settings for User Entity Instance: indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component
 16. Parameter Settings for User Entity Instance: indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component
 17. Parameter Settings for User Entity Instance: rh_lpm_dff0:inst14|lpm_ff:lpm_ff_component
 18. Parameter Settings for User Entity Instance: rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component
 19. Parameter Settings for User Entity Instance: rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component
 20. Parameter Settings for User Entity Instance: adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component
 21. Parameter Settings for User Entity Instance: rh_lpm_dff0:inst13|lpm_ff:lpm_ff_component
 22. Parameter Settings for User Entity Instance: rh_lpm_dff0:inst12|lpm_ff:lpm_ff_component
 23. lpm_mult Parameter Settings by Entity Instance
 24. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Dec 10 15:25:30 2007    ;
; Quartus II Version          ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name               ; rader_hilbert                            ;
; Top-level Entity Name       ; rader_hilbert                            ;
; Family                      ; Stratix                                  ;
; Total logic elements        ; 296                                      ;
; Total pins                  ; 51                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; DSP block 9-bit elements    ; 4                                        ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1S25F780C5       ;                    ;
; Top-level entity name                                              ; rader_hilbert      ; rader_hilbert      ;
; Family name                                                        ; Stratix            ; Stratix            ;
; Optimization Technique -- Stratix/Stratix GX                       ; Speed              ; Balanced           ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;