rader_hilbert.fit.smsg

FPGA开发光盘各章节实例的设计工程与源码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 10 15:25:31 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off rader_hilbert -c rader_hilbert
Info: Selected device EP1S25F780C5 for design "rader_hilbert"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S10F780C5 is compatible
    Info: Device EP1S10F780C5ES is compatible
    Info: Device EP1S20F780C5 is compatible
    Info: Device EP1S30F780C5 is compatible
    Info: Device EP1S30F780C5_HARDCOPY_FPGA_PROTOTYPE is compatible
    Info: Device EP1S40F780C5 is compatible
    Info: Device EP1S40F780C5_HARDCOPY_FPGA_PROTOTYPE is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location H12
Warning: No exact pin location assignment(s) for 51 pins of 51 total pins
    Info: Pin adenddly6 not assigned to an exact location on the device
    Info: Pin In[15] not assigned to an exact location on the device
    Info: Pin In[14] not assigned to an exact location on the device
    Info: Pin In[13] not assigned to an exact location on the device
    Info: Pin In[12] not assigned to an exact location on the device
    Info: Pin In[11] not assigned to an exact location on the device
    Info: Pin In[10] not assigned to an exact location on the device
    Info: Pin In[9] not assigned to an exact location on the device
    Info: Pin In[8] not assigned to an exact location on the device
    Info: Pin In[7] not assigned to an exact location on the device
    Info: Pin In[6] not assigned to an exact location on the device
    Info: Pin In[5] not assigned to an exact location on the device
    Info: Pin In[4] not assigned to an exact location on the device
    Info: Pin In[3] not assigned to an exact location on the device
    Info: Pin In[2] not assigned to an exact location on the device
    Info: Pin In[1] not assigned to an exact location on the device
    Info: Pin In[0] not assigned to an exact location on the device
    Info: Pin Qn[15] not assigned to an exact location on the device
    Info: Pin Qn[14] not assigned to an exact location on the device
    Info: Pin Qn[13] not assigned to an exact location on the device
    Info: Pin Qn[12] not assigned to an exact location on the device
    Info: Pin Qn[11] not assigned to an exact location on the device
    Info: Pin Qn[10] not assigned to an exact location on the device
    Info: Pin Qn[9] not assigned to an exact location on the device
    Info: Pin Qn[8] not assigned to an exact location on the device
    Info: Pin Qn[7] not assigned to an exact location on the device
    Info: Pin Qn[6] not assigned to an exact location on the device
    Info: Pin Qn[5] not assigned to an exact location on the device
    Info: Pin Qn[4] not assigned to an exact location on the device
    Info: Pin Qn[3] not assigned to an exact location on the device
    Info: Pin Qn[2] not assigned to an exact location on the device
    Info: Pin Qn[1] not assigned to an exact location on the device
    Info: Pin Qn[0] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin ad_end not assigned to an exact location on the device
    Info: Pin xn[15] not assigned to an exact location on the device
    Info: Pin xn[1] not assigned to an exact location on the device
    Info: Pin xn[2] not assigned to an exact location on the device
    Info: Pin xn[3] not assigned to an exact location on the device
    Info: Pin xn[4] not assigned to an exact location on the device
    Info: Pin xn[5] not assigned to an exact location on the device
    Info: Pin xn[6] not assigned to an exact location on the device
    Info: Pin xn[7] not assigned to an exact location on the device
    Info: Pin xn[8] not assigned to an exact location on the device
    Info: Pin xn[9] not assigned to an exact location on the device
    Info: Pin xn[10] not assigned to an exact location on the device
    Info: Pin xn[11] not assigned to an exact location on the device
    Info: Pin xn[12] not assigned to an exact location on the device
    Info: Pin xn[13] not assigned to an exact location on the device
    Info: Pin xn[14] not assigned to an exact location on the device
    Info: Pin xn[0] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN R25
Info: Automatically promoted some destinations of signal "oesel:inst1|evenen" to use Global clock
    Info: Destination "oesel:inst1|evenen" may be non-global or may not use global clock
    Info: Destination "sw1_4:inst23|ad_clk1" may be non-global or may not use global clock
    Info: Destination "sw1_4:inst26|cnt" may be non-global or may not use global clock
    Info: Destination "sw1_4:inst26|temp[15]~545" may be non-global or may not use global clock
    Info: Destination "sw1_4:inst23|cnt" may be non-global or may not use global clock
    Info: Destination "sw1_4:inst23|temp[15]~545" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 50 (unused VREF, 3.30 VCCIO, 17 input, 33 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  69 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  74 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  70 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  73 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  74 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  70 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  74 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  71 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:05
Info: Estimated most critical path is register to register delay of 10.551 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X73_Y8; Fanout = 4; REG Node = 'indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[8]'
    Info: 2: + IC(1.307 ns) + CELL(0.443 ns) = 1.750 ns; Loc. = LAB_X71_Y14; Fanout = 2; COMB Node = 'subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~331'
    Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 1.808 ns; Loc. = LAB_X71_Y14; Fanout = 2; COMB Node = 'subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~333'
    Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 1.866 ns; Loc. = LAB_X71_Y14; Fanout = 2; COMB Node = 'subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~335'
    Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 1.924 ns; Loc. = LAB_X71_Y14; Fanout = 2; COMB Node = 'subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~337'
    Info: 6: + IC(0.000 ns) + CELL(0.214 ns) = 2.138 ns; Loc. = LAB_X71_Y14; Fanout = 4; COMB Node = 'subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~339'
    Info: 7: + IC(0.000 ns) + CELL(0.469 ns) = 2.607 ns; Loc. = LAB_X71_Y14; Fanout = 32; COMB Node = 'subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~346'
    Info: 8: + IC(1.317 ns) + CELL(3.451 ns) = 7.375 ns; Loc. = DSPMULT_X68_Y15_N0; Fanout = 24; COMB Node = 'rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|mac_mult2~DATAOUT31'
    Info: 9: + IC(0.000 ns) + CELL(0.878 ns) = 8.253 ns; Loc. = DSPOUT_X69_Y9_N0; Fanout = 3; COMB Node = 'rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_v7u:auto_generated|result[16]'
    Info: 10: + IC(0.968 ns) + CELL(0.344 ns) = 9.565 ns; Loc. = LAB_X70_Y14; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~39'
    Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 9.623 ns; Loc. = LAB_X70_Y14; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~38'
    Info: 12: + IC(0.000 ns) + CELL(0.058 ns) = 9.681 ns; Loc. = LAB_X70_Y14; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~37'
    Info: 13: + IC(0.000 ns) + CELL(0.058 ns) = 9.739 ns; Loc. = LAB_X70_Y14; Fanout = 2; COMB Node = 'rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~36'
    Info: 14: + IC(0.000 ns) + CELL(0.214 ns) = 9.953 ns; Loc. = LAB_X70_Y14; Fanout = 3; COMB Node = 'rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~35'
    Info: 15: + IC(0.000 ns) + CELL(0.598 ns) = 10.551 ns; Loc. = LAB_X70_Y14; Fanout = 1; REG Node = 'rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]'
    Info: Total cell delay = 6.959 ns ( 65.96 % )
    Info: Total interconnect delay = 3.592 ns ( 34.04 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X68_Y12 to location X79_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 258 megabytes of memory during processing
    Info: Processing ended: Mon Dec 10 15:26:00 2007
    Info: Elapsed time: 00:00:29