📄 sw1_4.csf.rpt
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|R20 |-- |VCCIO1 |
|U28 |-- |VCCIO1 |
|AG28 |-- |VCCIO1 |
|Y15 |-- |VCCIO8 |
|AH17 |-- |VCCIO8 |
|AH27 |-- |VCCIO8 |
|Y14 |-- |VCCIO7 |
|AH2 |-- |VCCIO7 |
|AH12 |-- |VCCIO7 |
|R9 |-- |VCCIO6 |
|U1 |-- |VCCIO6 |
|AG1 |-- |VCCIO6 |
|B1 |-- |VCCIO5 |
|M1 |-- |VCCIO5 |
|P9 |-- |VCCIO5 |
|A2 |-- |VCCIO4 |
|A12 |-- |VCCIO4 |
|J14 |-- |VCCIO4 |
|A17 |-- |VCCIO3 |
|A27 |-- |VCCIO3 |
|J15 |-- |VCCIO3 |
|M14 |-- |VCCINT |
|N11 |-- |VCCINT |
|N13 |-- |VCCINT |
|N15 |-- |VCCINT |
|N17 |-- |VCCINT |
|P12 |-- |VCCINT |
|P14 |-- |VCCINT |
|P16 |-- |VCCINT |
|R13 |-- |VCCINT |
|R15 |-- |VCCINT |
|R17 |-- |VCCINT |
|T12 |-- |VCCINT |
|T14 |-- |VCCINT |
|T16 |-- |VCCINT |
|T18 |-- |VCCINT |
|U11 |-- |VCCINT |
|U13 |-- |VCCINT |
|U15 |-- |VCCINT |
|U17 |-- |VCCINT |
|V12 |-- |VCCINT |
|V16 |-- |VCCINT |
|C3 |-- |GND |
|C26 |-- |GND |
|L14 |-- |GND |
|L15 |-- |GND |
|M15 |-- |GND |
|N12 |-- |GND |
|N14 |-- |GND |
|N16 |-- |GND |
|N18 |-- |GND |
|P1 |-- |GND |
|P11 |-- |GND |
|P13 |-- |GND |
|P15 |-- |GND |
|P17 |-- |GND |
|P18 |-- |GND |
|P28 |-- |GND |
|R1 |-- |GND |
|R11 |-- |GND |
|R12 |-- |GND |
|R14 |-- |GND |
|R16 |-- |GND |
|R18 |-- |GND |
|AA16 |-- |GND |
|AC15 |-- |GND |
|G15 |-- |GND |
|H16 |-- |GND |
|R28 |-- |GND |
|T11 |-- |GND |
|T13 |-- |GND |
|T15 |-- |GND |
|T17 |-- |GND |
|U12 |-- |GND |
|U14 |-- |GND |
|U16 |-- |GND |
|U18 |-- |GND |
|V13 |-- |GND |
|V14 |-- |GND |
|V15 |-- |GND |
|V17 |-- |GND |
|AF3 |-- |GND |
|AF26 |-- |GND |
|AG2 |-- |GND |
|AG27 |-- |GND |
|AH14 |-- |GND |
|AH15 |-- |GND |
|A14 |-- |GND |
|A15 |-- |GND |
|B2 |-- |GND |
|B27 |-- |GND |
|P19 |-- |NC |
|E5 |-- |NC |
|E26 |-- |NC |
|E25 |-- |NC |
|D26 |-- |NC |
|D25 |-- |NC |
|AC26 |-- |NC |
|AC25 |-- |NC |
|AD26 |-- |NC |
|AD25 |-- |NC |
|AC3 |-- |NC |
|AD3 |-- |NC |
|AC4 |-- |NC |
|AD4 |-- |NC |
|E3 |-- |NC |
|E4 |-- |NC |
|D3 |-- |NC |
|D4 |-- |NC |
+-----+------+-------------+------------+
+-----------------------------------------------------------------------------+
|Control Signals |
+-----------------------------------------------------------------------------+
+---------+----------+-------+------------+------+--------------------+
|Name |Location |Fan-Out|Usage |Global|Global Resource Used|
+---------+----------+-------+------------+------+--------------------+
|clk |Unassigned|19 |Clock |no |-- |
|i~2 |Unassigned|2 |Clock enable|no |-- |
|temp[7]~0|Unassigned|8 |Clock enable|no |-- |
+---------+----------+-------+------------+------+--------------------+
+-----------------------------------------------------------------------------+
|Non-Global High Fan-Out Signals |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------------+-------+
|Name |Fan-Out|
+----------------------------------------------------------------------+-------+
|clk |19 |
|temp[7]~0 |8 |
|ad_clk |3 |
|lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[0]|3 |
|i~2 |2 |
|ad_clk1 |2 |
|lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[1]|2 |
|indata[0] |1 |
|indata[1] |1 |
|indata[2] |1 |
|indata[3] |1 |
|indata[4] |1 |
|indata[5] |1 |
|indata[6] |1 |
|indata[7] |1 |
|temp[0] |1 |
|temp[1] |1 |
|temp[2] |1 |
|temp[3] |1 |
|temp[4] |1 |
|temp[5] |1 |
|temp[6] |1 |
|temp[7] |1 |
|outdata[0]~reg0 |1 |
|outdata[1]~reg0 |1 |
|outdata[2]~reg0 |1 |
|outdata[3]~reg0 |1 |
|outdata[4]~reg0 |1 |
|outdata[5]~reg0 |1 |
|outdata[6]~reg0 |1 |
|outdata[7]~reg0 |1 |
+----------------------------------------------------------------------+-------+
+-----------------------------------------------------------------------------+
|Timing Settings |
+-----------------------------------------------------------------------------+
+-----------------+-----------+----------------+----------------------------------------------------------------+------------------+
|Assignment File |Source Name|Destination Name|Option |Setting |
+-----------------+-----------+----------------+----------------------------------------------------------------+------------------+
|rader_hilbert.psf|Include external delays to/from device pins in fmax calculations|Off |
|rader_hilbert.psf|Run All Timing Analyses |Off |
|rader_hilbert.psf|Ignore user-defined clock settings |Off |
|rader_hilbert.psf|Default hold multicycle |Same As Multicycle|
|rader_hilbert.psf|Cut off feedback from I/O pins |On |
|rader_hilbert.psf|Cut off clear and preset signal paths |On |
|rader_hilbert.psf|Cut off read during write signal paths |On |
|rader_hilbert.psf|Cut paths between unrelated clock domains |On |
|rader_hilbert.psf|Number of paths to report |200 |
|rader_hilbert.psf|Number of destination nodes to report |10 |
|rader_hilbert.psf|Number of source nodes to report per destination node |10 |
|rader_hilbert.psf|Maximum Strongly Connected Component loop size |50 |
|Device name |EP1S25F780C5 |
+-----------------+-----------+----------------+----------------------------------------------------------------+------------------+
+-----------------------------------------------------------------------------+
|fmax (not incl. delays to/from pins) |
+-----------------------------------------------------------------------------+
+-------------------------------------------------------------------------+-------------+------------------------------------------------------+
|Clock Name |Required fmax|Actual fmax (period) |
| -- Destination Register Name | | |
| -- Source Register Name | | |
+-------------------------------------------------------------------------+-------------+------------------------------------------------------+
|clk |None |292.14 MHz ( period = 3.423 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] |None |292.14 MHz ( period = 3.423 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |292.14 MHz ( period = 3.423 ns ) |
| -- ad_clk1 |None |330.47 MHz ( period = 3.026 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |Restricted to 422.12 MHz |
| -- temp[7] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[6] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[5] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[4] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[3] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[2] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[1] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- temp[0] |None |296.91 MHz ( period = 3.368 ns ) |
| -- ad_clk1 |None |296.91 MHz ( period = 3.368 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |306.75 MHz ( period = 3.260 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|None |317.86 MHz ( period = 3.146 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] |None |330.47 MHz ( period = 3.026 ns ) |
| -- ad_clk1 |None |330.47 MHz ( period = 3.026 ns ) |
| -- lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|None |Restricted to 422.12 MHz |
| -- Timing analysis results restricted. | |To change the limit use Timing Settings (Project menu)|
+-------------------------------------------------------------------------+-------------+------------------------------------------------------+
+-----------------------------------------------------------------------------+
|Register-to-Register fmax |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------+----------------------------------------------------------------+-----------------+----------------------+-------------+--------------------------------+
|Source Register Name |Destination Register Name |Source Clock Name|Destination Clock Name|Required fmax|Actual fmax (period) |
+----------------------------------------------------------------+----------------------------------------------------------------+-----------------+----------------------+-------------+--------------------------------+
|lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]|lpm_counter:cnt_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]|clk |clk |None |292.14 MHz ( period = 3.423 ns )|
|ad_clk1 |temp[7] |clk |clk |None |296.91 MHz ( period = 3.368 ns )|
|ad_clk1 |temp[6] |clk |clk |None |296.91 MHz ( period = 3.368 ns )|
|ad_clk1 |temp[5] |clk |clk |None |296.91 MHz ( period = 3.368 ns )|
|ad_clk1 |temp[4] |clk |clk |None |296.91 MHz ( period = 3.368 ns )|
|ad_clk1 |temp[3] |clk |clk |None |296.91 MHz ( period = 3.368 ns )|
|ad_clk1 ⌨️ 快捷键说明
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