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📄 sw1_4.csf.rpt

📁 FPGA开发光盘各章节实例的设计工程与源码
💻 RPT
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+-----------------------------------------------------------------------------+
|Input Pins                                                                   |
+-----------------------------------------------------------------------------+
+---------+----------+---------------------+------------------+------+--------------+-------------+--------------+---------------+--------+------------+---------+------------+-----------+
|Name     |Pin #     |Combinational Fan-Out|Registered Fan-Out|Global|Input Register|Power Up High|Slow Slew Rate|PCI I/O Enabled|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard|Termination|
+---------+----------+---------------------+------------------+------+--------------+-------------+--------------+---------------+--------+------------+---------+------------+-----------+
|ad_clk   |Unassigned|3                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|clk      |Unassigned|19                   |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[0]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[1]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[2]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[3]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[4]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[5]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[6]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|indata[7]|Unassigned|1                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
+---------+----------+---------------------+------------------+------+--------------+-------------+--------------+---------------+--------+------------+---------+------------+-----------+

+-----------------------------------------------------------------------------+
|Output Pins                                                                  |
+-----------------------------------------------------------------------------+
+----------+----------+---------------+----------------------+-------------+--------------+---------------+----------+--------+------------+---------+------------+----------------+-----------+
|Name      |Pin #     |Output Register|Output Enable Register|Power Up High|Slow Slew Rate|PCI I/O Enabled|Open Drain|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard|Current Strength|Termination|
+----------+----------+---------------+----------------------+-------------+--------------+---------------+----------+--------+------------+---------+------------+----------------+-----------+
|outdata[0]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[1]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[2]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[3]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[4]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[5]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[6]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|outdata[7]|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
+----------+----------+---------------+----------------------+-------------+--------------+---------------+----------+--------+------------+---------+------------+----------------+-----------+

+-----------------------------------------------------------------------------+
|Delay Chain Summary                                                          |
+-----------------------------------------------------------------------------+
+----------+--------+-----------+---------------------+-----------------------+--------------------------------------+-------------------------------+------------------------------+---+----+--------------------------+
|Name      |Pin Type|Pad to Core|Pad to Input Register|Core to Output Register|Clock Enable to Output Enable Register|Clock Enable to Output Register|Clock Enable to Input Register|TCO|TCOE|Falling Edge Output Enable|
+----------+--------+-----------+---------------------+-----------------------+--------------------------------------+-------------------------------+------------------------------+---+----+--------------------------+
|clk       |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[7] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|ad_clk    |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[6] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[5] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[4] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[3] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[2] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[1] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|indata[0] |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[7]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[6]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[5]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[4]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[3]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[2]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[1]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|outdata[0]|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
+----------+--------+-----------+---------------------+-----------------------+--------------------------------------+-------------------------------+------------------------------+---+----+--------------------------+

+-----------------------------------------------------------------------------+
|All Package Pins                                                             |
+-----------------------------------------------------------------------------+
+-----+------+-------------+------------+
|Pin #|Bank #|Usage        |I/O Standard|
+-----+------+-------------+------------+
|F24  |2     |GND*         |
|F23  |2     |GND*         |
|C27  |2     |GND*         |
|C28  |2     |GND*         |
|G23  |2     |GND*         |
|G24  |2     |GND*         |
|D27  |2     |GND*         |
|D28  |2     |GND*         |
|H24  |2     |GND*         |
|H23  |2     |GND*         |
|E27  |2     |GND*         |
|E28  |2     |GND*         |
|H22  |2     |GND*         |
|H21  |2     |GND*         |
|E24  |2     |GND          |
|F25  |2     |GND*         |
|F26  |2     |GND*         |
|J24  |2     |GND*         |
|J23  |2     |GND*         |
|F27  |2     |GND*         |
|F28  |2     |GND*         |
|K23  |2     |GND*         |
|K24  |2     |GND*         |
|G26  |2     |GND*         |
|G25  |2     |GND*         |
|J21  |2     |GND*         |
|J22  |2     |GND*         |
|G27  |2     |GND*         |
|G28  |2     |GND*         |
|K21  |2     |GND*         |
|K22  |2     |GND*         |
|H26  |2     |GND*         |
|H25  |2     |GND*         |
|L22  |2     |GND*         |
|L21  |2     |GND*         |
|H27  |2     |GND*         |
|H28  |2     |GND*         |
|L23  |2     |GND*         |
|L24  |2     |GND*         |
|J25  |2     |GND*         |
|J26  |2     |GND*         |
|L20  |2     |GND*         |
|L19  |2     |GND*         |
|J27  |2     |GND*         |
|J28  |2     |GND*         |
|M22  |2     |GND*         |
|M21  |2     |GND*         |
|K26  |2     |GND*         |
|K25  |2     |GND*         |
|M24  |2     |GND*         |
|M23  |2     |GND*         |
|K27  |2     |GND*         |
|K28  |2     |GND*         |
|M20  |2     |GND*         |
|M19  |2     |GND*         |
|K20  |2     |GND          |
|L25  |2     |GND*         |
|L26  |2     |GND*         |
|N26  |2     |GND*         |
|N25  |2     |GND*         |
|L27  |2     |GND*         |
|L28  |2     |GND*         |
|N24  |2     |GND*         |
|N23  |2     |GND*         |
|M25  |2     |GND*         |
|M26  |2     |GND*         |
|N22  |2     |GND*         |
|N21  |2     |GND*         |
|M27  |2     |GND*         |
|N28  |2     |GND*         |
|N20  |2     |GND*         |
|N19  |2     |GND*         |
|N27  |2     |GND+         |
|P27  |2     |GND+         |
|P26  |2     |GND*         |
|P25  |2     |GND+         |
|P23  |--    |VCCA_PLL1    |
|P24  |--    |GNDA_PLL1    |
|P21  |--    |VCCG_PLL1    |
|P22  |--    |GNDG_PLL1    |
|R23  |--    |VCCA_PLL2    |
|R24  |--    |GNDA_PLL2    |
|R21  |--    |VCCG_PLL2    |
|R22  |--    |GNDG_PLL2    |
|R27  |1     |GND+         |
|T27  |1     |GND+         |
|R25  |1     |GND+         |
|R26  |1     |GND*         |
|T28  |1     |GND*         |
|U27  |1     |GND*         |
|T21  |1     |GND*         |
|T22  |1     |GND*         |
|U26  |1     |GND*         |
|U25  |1     |GND*         |
|T19  |1     |GND*         |
|T20  |1     |GND*         |
|V27  |1     |GND*         |
|V28  |1     |GND*         |
|T23  |1     |GND*         |
|T24  |1     |GND*         |
|R19  |1     |GND          |
|V26  |1     |GND*         |
|V25  |1     |GND*         |
|T26  |1     |GND*         |
|T25  |1     |GND*         |
|W28  |1     |GND*         |
|W27  |1     |GND*         |
|U19  |1     |GND*         |
|U20  |1     |GND*         |
|W26  |1     |GND*         |
|W25  |1     |GND*         |
|U24  |1     |GND*         |
|U23  |1     |GND*         |
|Y28  |1     |GND*         |
|Y27  |1     |GND*         |
|U21  |1     |GND*         |
|U22  |1     |GND*         |
|Y26  |1     |GND*         |
|Y25  |1     |GND*         |
|V19  |1     |GND*         |
|V20  |1     |GND*         |
|AA28 |1     |GND*         |
|AA27 |1     |GND*         |
|V24  |1     |GND*         |
|V23  |1     |GND*         |
|AA25 |1     |GND*         |
|AA26 |1     |GND*         |
|V22  |1     |GND*         |
|V21  |1     |GND*         |
|W20  |1     |GND          |
|AB28 |1     |GND*         |
|AB27 |1     |GND*         |
|W23  |1     |GND*         |
|W24  |1     |GND*         |
|AB26 |1     |GND*         |
|AB25 |1     |GND*         |
|W21  |1     |GND*         |
|W22  |1     |GND*         |
|AC28 |1     |GND*         |
|AC27 |1     |GND*         |
|Y21  |1     |GND*         |
|Y22  |1     |GND*         |
|AD28 |1     |GND*         |
|AD27 |1     |GND*         |
|Y24  |1     |GND*         |
|Y23  |1     |GND*         |
|AE28 |1     |GND*         |
|AE27 |1     |GND*         |
|AA23 |1     |GND*         |
|AA24 |1     |GND*         |
|AF28 |1     |GND*         |
|AF27 |1     |GND*         |
|AA21 |1     |GND*         |
|AA22 |1     |GND*         |
|AB23 |1     |GND*         |
|AB24 |1     |GND*         |
|AE26 |1     |GND          |
|AC24 |8     |GND*         |
|AG26 |8     |GND*         |
|AC23 |8     |GND*         |
|AH26 |8     |GND*         |
|AG25 |8     |GND*         |
|AH25 |8     |GND*         |
|AB22 |8     |GND*         |
|AF25 |8     |GND*         |
|AF24 |8     |GND*         |
|AG24 |8     |GND*         |
|AE25 |8     |GND*         |
|AE24 |8     |GND*         |
|AH24 |8     |GND*         |
|AD24 |8     |GND*         |
|AG23 |8     |GND*         |
|AD22 |8     |GND          |
|AD23 |8     |GND*         |
|AF23 |8     |GND*         |
|AB21 |8     |GND*         |
|AH23 |8     |GND*         |
|AE22 |8     |GND*         |
|AE23 |8     |GND*         |

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