oesel.vhd

FPGA开发光盘各章节实例的设计工程与源码

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity oesel is 
  port(
	clk									   : in  std_logic;
	hlmux  						  	       : in  std_logic;
	odden								   : out std_logic;
	evenen                                 : out std_logic
		);
end oesel;
architecture behv of oesel is
	signal	hlmux1		: std_logic;
begin
process (clk)
	variable latchcnt: integer range 0 to 1;
begin
  if (clk'event and clk='1') then
		hlmux1<=hlmux;
   if (((not hlmux1) and hlmux)='1') then	
	if latchcnt=0 then
		odden <='1';
		evenen<='0';
	else
		odden <='0';
		evenen<='1';
	end if;
		latchcnt:=latchcnt+1;
    end if;			
  end if;
end process;
end behv;