rader_hilbert.eqn

FPGA开发光盘各章节实例的设计工程与源码

--L2L63Q is rd_contract:inst25|wconout[12]~reg0 at LC_X66_Y23_N4
--operation mode is arithmetic

L2L63Q_lut_out = X61_sout_node[4] $ !L2L33;
L2L63Q = DFFEA(L2L63Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--X31_cout[4] is rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4] at LC_X66_Y23_N4
--operation mode is arithmetic

X31_cout[4] = L2L73;


--L2L13Q is rd_contract:inst25|wconout[11]~reg0 at LC_X66_Y23_N3
--operation mode is arithmetic

L2L13Q_lut_out = X61_sout_node[3] $ L2L72;
L2L13Q = DFFEA(L2L13Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--L2L33 is rd_contract:inst25|wconout[11]~reg0COUT0COUT0 at LC_X66_Y23_N3
--operation mode is arithmetic

L2L33_cout_0 = !L2L72 # !X61_sout_node[3];
L2L33 = CARRY(L2L33_cout_0);

--L2L53 is rd_contract:inst25|wconout[11]~reg0COUT1COUT1 at LC_X66_Y23_N3
--operation mode is arithmetic

L2L53_cout_1 = !L2L03 # !X61_sout_node[3];
L2L53 = CARRY(L2L53_cout_1);


--L2L42Q is rd_contract:inst25|wconout[10]~reg0 at LC_X66_Y23_N2
--operation mode is arithmetic

L2L42Q_lut_out = X61_sout_node[2] $ !L2L02;
L2L42Q = DFFEA(L2L42Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--L2L72 is rd_contract:inst25|wconout[10]~reg0COUT0COUT0COUT0 at LC_X66_Y23_N2
--operation mode is arithmetic

L2L72_cout_0 = X61_sout_node[2] & !L2L02;
L2L72 = CARRY(L2L72_cout_0);

--L2L03 is rd_contract:inst25|wconout[10]~reg0COUT1COUT1COUT1 at LC_X66_Y23_N2
--operation mode is arithmetic

L2L03_cout_1 = X61_sout_node[2] & !L2L32;
L2L03 = CARRY(L2L03_cout_1);


--L2L71Q is rd_contract:inst25|wconout[9]~reg0 at LC_X66_Y23_N1
--operation mode is arithmetic

L2L71Q_lut_out = X61_sout_node[1] $ L2L31;
L2L71Q = DFFEA(L2L71Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--L2L02 is rd_contract:inst25|wconout[9]~reg0COUT0COUT0COUT0 at LC_X66_Y23_N1
--operation mode is arithmetic

L2L02_cout_0 = !L2L31 # !X61_sout_node[1];
L2L02 = CARRY(L2L02_cout_0);

--L2L32 is rd_contract:inst25|wconout[9]~reg0COUT1COUT1COUT1 at LC_X66_Y23_N1
--operation mode is arithmetic

L2L32_cout_1 = !L2L61 # !X61_sout_node[1];
L2L32 = CARRY(L2L32_cout_1);


--L2L01Q is rd_contract:inst25|wconout[8]~reg0 at LC_X66_Y23_N0
--operation mode is arithmetic

L2L01Q_lut_out = X01_sout_node[16] $ X61_sout_node[0];
L2L01Q = DFFEA(L2L01Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--L2L31 is rd_contract:inst25|wconout[8]~reg0COUT0COUT0COUT0 at LC_X66_Y23_N0
--operation mode is arithmetic

L2L31_cout_0 = X01_sout_node[16] & X61_sout_node[0];
L2L31 = CARRY(L2L31_cout_0);

--L2L61 is rd_contract:inst25|wconout[8]~reg0COUT1COUT1COUT1 at LC_X66_Y23_N0
--operation mode is arithmetic

L2L61_cout_1 = X01_sout_node[16] & X61_sout_node[0];
L2L61 = CARRY(L2L61_cout_1);


--L2L9Q is rd_contract:inst25|wconout[7]~reg0 at LC_X70_Y25_N6
--operation mode is normal

L2L9Q_lut_out = X01_sout_node[15];
L2L9Q = DFFEA(L2L9Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L8Q is rd_contract:inst25|wconout[6]~reg0 at LC_X70_Y25_N5
--operation mode is normal

L2L8Q_lut_out = X01_sout_node[14];
L2L8Q = DFFEA(L2L8Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L7Q is rd_contract:inst25|wconout[5]~reg0 at LC_X66_Y23_N8
--operation mode is normal

L2L7Q_lut_out = X01_sout_node[13];
L2L7Q = DFFEA(L2L7Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L6Q is rd_contract:inst25|wconout[4]~reg0 at LC_X70_Y25_N7
--operation mode is normal

L2L6Q_lut_out = X01_sout_node[12];
L2L6Q = DFFEA(L2L6Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L5Q is rd_contract:inst25|wconout[3]~reg0 at LC_X70_Y25_N2
--operation mode is normal

L2L5Q_lut_out = X01_sout_node[11];
L2L5Q = DFFEA(L2L5Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L4Q is rd_contract:inst25|wconout[2]~reg0 at LC_X70_Y25_N9
--operation mode is normal

L2L4Q_lut_out = X01_sout_node[10];
L2L4Q = DFFEA(L2L4Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L3Q is rd_contract:inst25|wconout[1]~reg0 at LC_X70_Y25_N8
--operation mode is normal

L2L3Q_lut_out = X01_sout_node[9];
L2L3Q = DFFEA(L2L3Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--L2L2Q is rd_contract:inst25|wconout[0]~reg0 at LC_X71_Y23_N2
--operation mode is normal

L2L2Q_lut_out = X01_sout_node[8];
L2L2Q = DFFEA(L2L2Q_lut_out, GLOBAL(clk), VCC, L2L1, , );


--G1_inst12 is rd_contr:inst10|inst12 at LC_X1_Y25_N2
--operation mode is normal

G1_inst12_lut_out = G1_inst9;
G1_inst12 = DFFEA(G1_inst12_lut_out, GLOBAL(clk), VCC, , , );


--G1_inst is rd_contr:inst10|inst at LC_X1_Y25_N3
--operation mode is normal

G1_inst_lut_out = ad_end;
G1_inst = DFFEA(G1_inst_lut_out, GLOBAL(clk), VCC, , , );


--C1_hlmux1 is oesel:inst1|hlmux1 at LC_X1_Y25_N9
--operation mode is normal

C1_hlmux1_lut_out = !G1_inst & G1_inst3;
C1_hlmux1 = DFFEA(C1_hlmux1_lut_out, GLOBAL(clk), VCC, , , );


--C1L2 is oesel:inst1|i~1 at LC_X1_Y25_N7
--operation mode is normal

G1_inst3_qfbk = G1_inst3;
C1L2 = !G1_inst & !C1_hlmux1 & G1_inst3_qfbk;

--G1_inst3 is rd_contr:inst10|inst3 at LC_X1_Y25_N7
--operation mode is normal

G1_inst3_sload_eqn = (VCC & G1_inst) # (GND & C1L2);
G1_inst3 = DFFEA(G1_inst3_sload_eqn, GLOBAL(clk), VCC, , , );


--M2L3 is sw1_4:inst26|i~1 at LC_X9_Y22_N2
--operation mode is normal

M2L3 = !M2_ad_clk1 & C1L3Q;


--X7_sout_node[6] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6] at LC_X12_Y16_N6
--operation mode is arithmetic

X7_sout_node[6]_carry_eqn = (!X7_cout[4] & X7L62) # (X7_cout[4] & X7L72);
X7_sout_node[6]_lut_out = F1L8Q $ S2_result[22] $ !X7_sout_node[6]_carry_eqn;
X7_sout_node[6] = DFFEA(X7_sout_node[6]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7L92 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~COUT0 at LC_X12_Y16_N6
--operation mode is arithmetic

X7L92_cout_0 = F1L8Q & (S2_result[22] # !X7L62) # !F1L8Q & S2_result[22] & !X7L62;
X7L92 = CARRY(X7L92_cout_0);

--X7L03 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~COUT1 at LC_X12_Y16_N6
--operation mode is arithmetic

X7L03_cout_1 = F1L8Q & (S2_result[22] # !X7L72) # !F1L8Q & S2_result[22] & !X7L72;
X7L03 = CARRY(X7L03_cout_1);


--X7_sout_node[5] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5] at LC_X12_Y16_N5
--operation mode is arithmetic

X7_sout_node[5]_carry_eqn = (!X7_cout[4] & GND) # (X7_cout[4] & VCC);
X7_sout_node[5]_lut_out = F1L8Q $ S2_result[21] $ X7_sout_node[5]_carry_eqn;
X7_sout_node[5] = DFFEA(X7_sout_node[5]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7L62 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~COUT0 at LC_X12_Y16_N5
--operation mode is arithmetic

X7L62_cout_0 = F1L8Q & !S2_result[21] & VCC # !F1L8Q & (VCC # !S2_result[21]);
X7L62 = CARRY(X7L62_cout_0);

--X7L72 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~COUT1 at LC_X12_Y16_N5
--operation mode is arithmetic

X7L72_cout_1 = F1L8Q & !S2_result[21] & GND # !F1L8Q & (GND # !S2_result[21]);
X7L72 = CARRY(X7L72_cout_1);


--X7_sout_node[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4] at LC_X12_Y16_N4
--operation mode is arithmetic

X7_sout_node[4]_lut_out = F1L8Q $ S2_result[20] $ !X7L02;
X7_sout_node[4] = DFFEA(X7_sout_node[4]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|cout[4] at LC_X12_Y16_N4
--operation mode is arithmetic

X7_cout[4] = X7L32;


--X7_sout_node[3] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] at LC_X12_Y16_N3
--operation mode is arithmetic

X7_sout_node[3]_lut_out = F1L8Q $ S2_result[19] $ X7L71;
X7_sout_node[3] = DFFEA(X7_sout_node[3]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7L02 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~COUT0 at LC_X12_Y16_N3
--operation mode is arithmetic

X7L02_cout_0 = F1L8Q & !S2_result[19] & !X7L71 # !F1L8Q & (!X7L71 # !S2_result[19]);
X7L02 = CARRY(X7L02_cout_0);

--X7L12 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~COUT1 at LC_X12_Y16_N3
--operation mode is arithmetic

X7L12_cout_1 = F1L8Q & !S2_result[19] & !X7L81 # !F1L8Q & (!X7L81 # !S2_result[19]);
X7L12 = CARRY(X7L12_cout_1);


--X7_sout_node[2] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2] at LC_X12_Y16_N2
--operation mode is arithmetic

X7_sout_node[2]_lut_out = F1L8Q $ S2_result[18] $ !X7L41;
X7_sout_node[2] = DFFEA(X7_sout_node[2]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7L71 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~COUT0 at LC_X12_Y16_N2
--operation mode is arithmetic

X7L71_cout_0 = F1L8Q & (S2_result[18] # !X7L41) # !F1L8Q & S2_result[18] & !X7L41;
X7L71 = CARRY(X7L71_cout_0);

--X7L81 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~COUT1 at LC_X12_Y16_N2
--operation mode is arithmetic

X7L81_cout_1 = F1L8Q & (S2_result[18] # !X7L51) # !F1L8Q & S2_result[18] & !X7L51;
X7L81 = CARRY(X7L81_cout_1);


--X7_sout_node[1] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1] at LC_X12_Y16_N1
--operation mode is arithmetic

X7_sout_node[1]_lut_out = F1L8Q $ S2_result[17] $ X7L11;
X7_sout_node[1] = DFFEA(X7_sout_node[1]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7L41 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~COUT0 at LC_X12_Y16_N1
--operation mode is arithmetic

X7L41_cout_0 = F1L8Q & !S2_result[17] & !X7L11 # !F1L8Q & (!X7L11 # !S2_result[17]);
X7L41 = CARRY(X7L41_cout_0);

--X7L51 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~COUT1 at LC_X12_Y16_N1
--operation mode is arithmetic

X7L51_cout_1 = F1L8Q & !S2_result[17] & !X7L21 # !F1L8Q & (!X7L21 # !S2_result[17]);
X7L51 = CARRY(X7L51_cout_1);


--X7_sout_node[0] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] at LC_X12_Y16_N0
--operation mode is arithmetic

X7_sout_node[0]_lut_out = F1L8Q $ S2_result[16];
X7_sout_node[0] = DFFEA(X7_sout_node[0]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X7L11 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~COUT0 at LC_X12_Y16_N0
--operation mode is arithmetic

X7L11_cout_0 = F1L8Q & S2_result[16];
X7L11 = CARRY(X7L11_cout_0);

--X7L21 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~COUT1 at LC_X12_Y16_N0
--operation mode is arithmetic

X7L21_cout_1 = F1L8Q & S2_result[16];
X7L21 = CARRY(X7L21_cout_1);


--X2_sout_node[15] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15] at LC_X12_Y18_N7
--operation mode is arithmetic

X2_sout_node[15]_carry_eqn = (!X2_cout[12] & X2L08) # (X2_cout[12] & X2L18);
X2_sout_node[15]_lut_out = F1L8Q $ S2_result[15] $ X2_sout_node[15]_carry_eqn;
X2_sout_node[15] = DFFEA(X2_sout_node[15]_lut_out, GLOBAL(clk), VCC, E1_inst9, , );

--X2L38 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]~COUT0 at LC_X12_Y18_N7
--operation mode is arithmetic

X2L38_cout_0 = F1L8Q & !S2_result[15] & !X2L08 # !F1L8Q & (!X2L08 # !S2_result[15]);
X2L38 = CARRY(X2L38_cout_0);

--X2L48 is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]~COUT1 at LC_X12_Y18_N7
--operation mode is arithmetic

X2L48_cout_1 = F1L8Q & !S2_result[15] & !X2L18 # !F1L8Q & (!X2L18 # !S2_result[15]);
X2L48 = CARRY(X2L48_cout_1);


--L1L2 is rd_contract:inst22|i~1 at LC_X33_Y21_N4
--operation mode is normal

E1_inst29_qfbk = E1_inst29;
L1L2 = E1_inst29_qfbk & !L1_conclk1;

--E1_inst29 is contrIQ:inst4|in