rader_hilbert.eqn

FPGA开发光盘各章节实例的设计工程与源码

M1_temp[10]_lut_out = L2L42Q;
M1_temp[10] = DFFEA(M1_temp[10]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[9] is sw1_4:inst23|temp[9] at LC_X71_Y23_N4
--operation mode is normal

M1_temp[9]_lut_out = L2L71Q;
M1_temp[9] = DFFEA(M1_temp[9]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[8] is sw1_4:inst23|temp[8] at LC_X71_Y23_N5
--operation mode is normal

M1_temp[8]_lut_out = L2L01Q;
M1_temp[8] = DFFEA(M1_temp[8]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[7] is sw1_4:inst23|temp[7] at LC_X70_Y25_N4
--operation mode is normal

M1_temp[7]_lut_out = L2L9Q;
M1_temp[7] = DFFEA(M1_temp[7]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[6] is sw1_4:inst23|temp[6] at LC_X71_Y25_N5
--operation mode is normal

M1_temp[6]_lut_out = L2L8Q;
M1_temp[6] = DFFEA(M1_temp[6]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[5] is sw1_4:inst23|temp[5] at LC_X66_Y26_N4
--operation mode is normal

M1_temp[5]_lut_out = L2L7Q;
M1_temp[5] = DFFEA(M1_temp[5]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[4] is sw1_4:inst23|temp[4] at LC_X70_Y22_N2
--operation mode is normal

M1_temp[4]_lut_out = L2L6Q;
M1_temp[4] = DFFEA(M1_temp[4]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[3] is sw1_4:inst23|temp[3] at LC_X71_Y25_N7
--operation mode is normal

M1_temp[3]_lut_out = L2L5Q;
M1_temp[3] = DFFEA(M1_temp[3]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[2] is sw1_4:inst23|temp[2] at LC_X71_Y25_N8
--operation mode is normal

M1_temp[2]_lut_out = L2L4Q;
M1_temp[2] = DFFEA(M1_temp[2]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[1] is sw1_4:inst23|temp[1] at LC_X70_Y26_N2
--operation mode is normal

M1_temp[1]_lut_out = L2L3Q;
M1_temp[1] = DFFEA(M1_temp[1]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--M1_temp[0] is sw1_4:inst23|temp[0] at LC_X71_Y23_N6
--operation mode is normal

M1_temp[0]_lut_out = L2L2Q;
M1_temp[0] = DFFEA(M1_temp[0]_lut_out, GLOBAL(clk), VCC, M1L63, , );


--G1_inst17 is rd_contr:inst10|inst17 at LC_X1_Y25_N4
--operation mode is normal

G1_inst17_lut_out = G1_inst12;
G1_inst17 = DFFEA(G1_inst17_lut_out, GLOBAL(clk), VCC, , , );


--C1L3Q is oesel:inst1|odden~reg0 at LC_X1_Y25_N5
--operation mode is normal

C1L3Q_lut_out = !C1L3Q;
C1L3Q = DFFEA(C1L3Q_lut_out, GLOBAL(clk), VCC, C1L2, , );


--M2_cnt is sw1_4:inst26|cnt at LC_X9_Y22_N5
--operation mode is normal

M2_cnt_lut_out = !M2_cnt;
M2_cnt = DFFEA(M2_cnt_lut_out, GLOBAL(clk), VCC, M2L3, , );


--M2L73 is sw1_4:inst26|temp[15]~0 at LC_X9_Y22_N4
--operation mode is normal

M2L73 = C1L3Q & !M2_cnt & !M2_ad_clk1;


--L1L74Q is rd_contract:inst22|wconout[14]~reg0 at LC_X12_Y17_N6
--operation mode is arithmetic

L1L74Q_carry_eqn = (!X4_cout[4] & L1L34) # (X4_cout[4] & L1L64);
L1L74Q_lut_out = X7_sout_node[6] $ !L1L74Q_carry_eqn;
L1L74Q = DFFEA(L1L74Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--L1L05 is rd_contract:inst22|wconout[14]~reg0COUT0COUT0COUT0 at LC_X12_Y17_N6
--operation mode is arithmetic

L1L05_cout_0 = X7_sout_node[6] & !L1L34;
L1L05 = CARRY(L1L05_cout_0);

--L1L35 is rd_contract:inst22|wconout[14]~reg0COUT1COUT1COUT1 at LC_X12_Y17_N6
--operation mode is arithmetic

L1L35_cout_1 = X7_sout_node[6] & !L1L64;
L1L35 = CARRY(L1L35_cout_1);


--L1L04Q is rd_contract:inst22|wconout[13]~reg0 at LC_X12_Y17_N5
--operation mode is arithmetic

L1L04Q_carry_eqn = (!X4_cout[4] & GND) # (X4_cout[4] & VCC);
L1L04Q_lut_out = X7_sout_node[5] $ L1L04Q_carry_eqn;
L1L04Q = DFFEA(L1L04Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--L1L34 is rd_contract:inst22|wconout[13]~reg0COUT0COUT0COUT0 at LC_X12_Y17_N5
--operation mode is arithmetic

L1L34_cout_0 = VCC # !X7_sout_node[5];
L1L34 = CARRY(L1L34_cout_0);

--L1L64 is rd_contract:inst22|wconout[13]~reg0COUT1COUT1COUT1 at LC_X12_Y17_N5
--operation mode is arithmetic

L1L64_cout_1 = GND # !X7_sout_node[5];
L1L64 = CARRY(L1L64_cout_1);


--L1L73Q is rd_contract:inst22|wconout[12]~reg0 at LC_X12_Y17_N4
--operation mode is arithmetic

L1L73Q_lut_out = X7_sout_node[4] $ !L1L43;
L1L73Q = DFFEA(L1L73Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--X4_cout[4] is rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4] at LC_X12_Y17_N4
--operation mode is arithmetic

X4_cout[4] = L1L83;


--L1L23Q is rd_contract:inst22|wconout[11]~reg0 at LC_X12_Y17_N3
--operation mode is arithmetic

L1L23Q_lut_out = X7_sout_node[3] $ L1L82;
L1L23Q = DFFEA(L1L23Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--L1L43 is rd_contract:inst22|wconout[11]~reg0COUT0COUT0 at LC_X12_Y17_N3
--operation mode is arithmetic

L1L43_cout_0 = !L1L82 # !X7_sout_node[3];
L1L43 = CARRY(L1L43_cout_0);

--L1L63 is rd_contract:inst22|wconout[11]~reg0COUT1COUT1 at LC_X12_Y17_N3
--operation mode is arithmetic

L1L63_cout_1 = !L1L13 # !X7_sout_node[3];
L1L63 = CARRY(L1L63_cout_1);


--L1L52Q is rd_contract:inst22|wconout[10]~reg0 at LC_X12_Y17_N2
--operation mode is arithmetic

L1L52Q_lut_out = X7_sout_node[2] $ !L1L12;
L1L52Q = DFFEA(L1L52Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--L1L82 is rd_contract:inst22|wconout[10]~reg0COUT0COUT0COUT0 at LC_X12_Y17_N2
--operation mode is arithmetic

L1L82_cout_0 = X7_sout_node[2] & !L1L12;
L1L82 = CARRY(L1L82_cout_0);

--L1L13 is rd_contract:inst22|wconout[10]~reg0COUT1COUT1COUT1 at LC_X12_Y17_N2
--operation mode is arithmetic

L1L13_cout_1 = X7_sout_node[2] & !L1L42;
L1L13 = CARRY(L1L13_cout_1);


--L1L81Q is rd_contract:inst22|wconout[9]~reg0 at LC_X12_Y17_N1
--operation mode is arithmetic

L1L81Q_lut_out = X7_sout_node[1] $ L1L41;
L1L81Q = DFFEA(L1L81Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--L1L12 is rd_contract:inst22|wconout[9]~reg0COUT0COUT0COUT0 at LC_X12_Y17_N1
--operation mode is arithmetic

L1L12_cout_0 = !L1L41 # !X7_sout_node[1];
L1L12 = CARRY(L1L12_cout_0);

--L1L42 is rd_contract:inst22|wconout[9]~reg0COUT1COUT1COUT1 at LC_X12_Y17_N1
--operation mode is arithmetic

L1L42_cout_1 = !L1L71 # !X7_sout_node[1];
L1L42 = CARRY(L1L42_cout_1);


--L1L11Q is rd_contract:inst22|wconout[8]~reg0 at LC_X12_Y17_N0
--operation mode is arithmetic

L1L11Q_lut_out = X7_sout_node[0] $ X2_sout_node[16];
L1L11Q = DFFEA(L1L11Q_lut_out, GLOBAL(clk), VCC, L1L2, , );

--L1L41 is rd_contract:inst22|wconout[8]~reg0COUT0COUT0COUT0 at LC_X12_Y17_N0
--operation mode is arithmetic

L1L41_cout_0 = X7_sout_node[0] & X2_sout_node[16];
L1L41 = CARRY(L1L41_cout_0);

--L1L71 is rd_contract:inst22|wconout[8]~reg0COUT1COUT1COUT1 at LC_X12_Y17_N0
--operation mode is arithmetic

L1L71_cout_1 = X7_sout_node[0] & X2_sout_node[16];
L1L71 = CARRY(L1L71_cout_1);


--L1L01Q is rd_contract:inst22|wconout[7]~reg0 at LC_X12_Y20_N4
--operation mode is normal

L1L01Q_lut_out = X2_sout_node[15];
L1L01Q = DFFEA(L1L01Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L9Q is rd_contract:inst22|wconout[6]~reg0 at LC_X12_Y20_N5
--operation mode is normal

L1L9Q_lut_out = X2_sout_node[14];
L1L9Q = DFFEA(L1L9Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L8Q is rd_contract:inst22|wconout[5]~reg0 at LC_X12_Y20_N7
--operation mode is normal

L1L8Q_lut_out = X2_sout_node[13];
L1L8Q = DFFEA(L1L8Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L7Q is rd_contract:inst22|wconout[4]~reg0 at LC_X12_Y20_N3
--operation mode is normal

L1L7Q_lut_out = X2_sout_node[12];
L1L7Q = DFFEA(L1L7Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L6Q is rd_contract:inst22|wconout[3]~reg0 at LC_X12_Y20_N0
--operation mode is normal

L1L6Q_lut_out = X2_sout_node[11];
L1L6Q = DFFEA(L1L6Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L5Q is rd_contract:inst22|wconout[2]~reg0 at LC_X9_Y20_N9
--operation mode is normal

L1L5Q_lut_out = X2_sout_node[10];
L1L5Q = DFFEA(L1L5Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L4Q is rd_contract:inst22|wconout[1]~reg0 at LC_X9_Y20_N5
--operation mode is normal

L1L4Q_lut_out = X2_sout_node[9];
L1L4Q = DFFEA(L1L4Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--L1L3Q is rd_contract:inst22|wconout[0]~reg0 at LC_X12_Y18_N9
--operation mode is normal

L1L3Q_lut_out = X2_sout_node[8];
L1L3Q = DFFEA(L1L3Q_lut_out, GLOBAL(clk), VCC, L1L2, , );


--M1_cnt is sw1_4:inst23|cnt at LC_X66_Y22_N4
--operation mode is normal

M1_cnt_lut_out = !M1_cnt;
M1_cnt = DFFEA(M1_cnt_lut_out, GLOBAL(clk), VCC, M1L2, , );


--M1L63 is sw1_4:inst23|temp[15]~0 at LC_X66_Y22_N2
--operation mode is normal

M2_ad_clk1_qfbk = M2_ad_clk1;
M1L63 = !C1L3Q & M2_ad_clk1_qfbk & !M1_cnt;

--M2_ad_clk1 is sw1_4:inst26|ad_clk1 at LC_X66_Y22_N2
--operation mode is normal

M2_ad_clk1_sload_eqn = (VCC & C1L3Q) # (GND & M1L63);
M2_ad_clk1 = DFFEA(M2_ad_clk1_sload_eqn, GLOBAL(clk), VCC, , , );


--L2L64Q is rd_contract:inst25|wconout[14]~reg0 at LC_X66_Y23_N6
--operation mode is arithmetic

L2L64Q_carry_eqn = (!X31_cout[4] & L2L24) # (X31_cout[4] & L2L54);
L2L64Q_lut_out = X61_sout_node[6] $ !L2L64Q_carry_eqn;
L2L64Q = DFFEA(L2L64Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--L2L94 is rd_contract:inst25|wconout[14]~reg0COUT0COUT0COUT0 at LC_X66_Y23_N6
--operation mode is arithmetic

L2L94_cout_0 = X61_sout_node[6] & !L2L24;
L2L94 = CARRY(L2L94_cout_0);

--L2L25 is rd_contract:inst25|wconout[14]~reg0COUT1COUT1COUT1 at LC_X66_Y23_N6
--operation mode is arithmetic

L2L25_cout_1 = X61_sout_node[6] & !L2L54;
L2L25 = CARRY(L2L25_cout_1);


--L2L93Q is rd_contract:inst25|wconout[13]~reg0 at LC_X66_Y23_N5
--operation mode is arithmetic

L2L93Q_carry_eqn = (!X31_cout[4] & GND) # (X31_cout[4] & VCC);
L2L93Q_lut_out = X61_sout_node[5] $ L2L93Q_carry_eqn;
L2L93Q = DFFEA(L2L93Q_lut_out, GLOBAL(clk), VCC, L2L1, , );

--L2L24 is rd_contract:inst25|wconout[13]~reg0COUT0COUT0COUT0 at LC_X66_Y23_N5
--operation mode is arithmetic

L2L24_cout_0 = VCC # !X61_sout_node[5];
L2L24 = CARRY(L2L24_cout_0);

--L2L54 is rd_contract:inst25|wconout[13]~reg0COUT1COUT1COUT1 at LC_X66_Y23_N5
--operation mode is arithmetic

L2L54_cout_1 = GND # !X61_sout_node[5];
L2L54 = CARRY(L2L54_cout_1);