oesel.csf.rpt

FPGA开发光盘各章节实例的设计工程与源码

|C17  |3     |GND*         |
|J18  |3     |GND*         |
|K19  |3     |GND*         |
|A18  |3     |GND*         |
|C18  |3     |GND*         |
|G18  |3     |GND*         |
|D18  |3     |GND*         |
|B18  |3     |GND*         |
|A19  |3     |GND*         |
|J19  |3     |GND*         |
|B19  |3     |GND*         |
|C19  |3     |GND*         |
|E19  |3     |GND*         |
|E20  |3     |GND          |
|F19  |3     |GND*         |
|G19  |3     |GND*         |
|D19  |3     |GND*         |
|H19  |3     |GND*         |
|B20  |3     |GND*         |
|G20  |--    |GND          |
|A20  |3     |GND*         |
|C20  |3     |GND*         |
|D20  |3     |GND*         |
|A21  |3     |GND*         |
|J20  |3     |GND*         |
|B21  |3     |GND*         |
|C21  |3     |GND*         |
|D21  |3     |GND*         |
|E21  |3     |GND*         |
|H20  |3     |GND*         |
|B22  |3     |GND*         |
|A22  |3     |GND*         |
|C22  |3     |GND*         |
|D23  |3     |GND*         |
|D22  |3     |GND*         |
|A23  |3     |GND*         |
|C23  |3     |GND*         |
|E23  |3     |GND*         |
|E22  |3     |GND          |
|B23  |3     |GND*         |
|F20  |3     |GND*         |
|A24  |3     |GND*         |
|C25  |3     |GND*         |
|F21  |3     |GND*         |
|A25  |3     |GND*         |
|C24  |3     |GND*         |
|G21  |3     |GND*         |
|D24  |3     |GND*         |
|G22  |3     |GND*         |
|B24  |3     |GND*         |
|B25  |3     |GND*         |
|A26  |3     |GND*         |
|F22  |3     |GND*         |
|B26  |3     |GND*         |
|B28  |--    |VCCIO2       |
|M28  |--    |VCCIO2       |
|P20  |--    |VCCIO2       |
|R20  |--    |VCCIO1       |
|U28  |--    |VCCIO1       |
|AG28 |--    |VCCIO1       |
|Y15  |--    |VCCIO8       |
|AH17 |--    |VCCIO8       |
|AH27 |--    |VCCIO8       |
|Y14  |--    |VCCIO7       |
|AH2  |--    |VCCIO7       |
|AH12 |--    |VCCIO7       |
|R9   |--    |VCCIO6       |
|U1   |--    |VCCIO6       |
|AG1  |--    |VCCIO6       |
|B1   |--    |VCCIO5       |
|M1   |--    |VCCIO5       |
|P9   |--    |VCCIO5       |
|A2   |--    |VCCIO4       |
|A12  |--    |VCCIO4       |
|J14  |--    |VCCIO4       |
|A17  |--    |VCCIO3       |
|A27  |--    |VCCIO3       |
|J15  |--    |VCCIO3       |
|M14  |--    |VCCINT       |
|N11  |--    |VCCINT       |
|N13  |--    |VCCINT       |
|N15  |--    |VCCINT       |
|N17  |--    |VCCINT       |
|P12  |--    |VCCINT       |
|P14  |--    |VCCINT       |
|P16  |--    |VCCINT       |
|R13  |--    |VCCINT       |
|R15  |--    |VCCINT       |
|R17  |--    |VCCINT       |
|T12  |--    |VCCINT       |
|T14  |--    |VCCINT       |
|T16  |--    |VCCINT       |
|T18  |--    |VCCINT       |
|U11  |--    |VCCINT       |
|U13  |--    |VCCINT       |
|U15  |--    |VCCINT       |
|U17  |--    |VCCINT       |
|V12  |--    |VCCINT       |
|V16  |--    |VCCINT       |
|C3   |--    |GND          |
|C26  |--    |GND          |
|L14  |--    |GND          |
|L15  |--    |GND          |
|M15  |--    |GND          |
|N12  |--    |GND          |
|N14  |--    |GND          |
|N16  |--    |GND          |
|N18  |--    |GND          |
|P1   |--    |GND          |
|P11  |--    |GND          |
|P13  |--    |GND          |
|P15  |--    |GND          |
|P17  |--    |GND          |
|P18  |--    |GND          |
|P28  |--    |GND          |
|R1   |--    |GND          |
|R11  |--    |GND          |
|R12  |--    |GND          |
|R14  |--    |GND          |
|R16  |--    |GND          |
|R18  |--    |GND          |
|AA16 |--    |GND          |
|AC15 |--    |GND          |
|G15  |--    |GND          |
|H16  |--    |GND          |
|R28  |--    |GND          |
|T11  |--    |GND          |
|T13  |--    |GND          |
|T15  |--    |GND          |
|T17  |--    |GND          |
|U12  |--    |GND          |
|U14  |--    |GND          |
|U16  |--    |GND          |
|U18  |--    |GND          |
|V13  |--    |GND          |
|V14  |--    |GND          |
|V15  |--    |GND          |
|V17  |--    |GND          |
|AF3  |--    |GND          |
|AF26 |--    |GND          |
|AG2  |--    |GND          |
|AG27 |--    |GND          |
|AH14 |--    |GND          |
|AH15 |--    |GND          |
|A14  |--    |GND          |
|A15  |--    |GND          |
|B2   |--    |GND          |
|B27  |--    |GND          |
|P19  |--    |NC           |
|E5   |--    |NC           |
|E26  |--    |NC           |
|E25  |--    |NC           |
|D26  |--    |NC           |
|D25  |--    |NC           |
|AC26 |--    |NC           |
|AC25 |--    |NC           |
|AD26 |--    |NC           |
|AD25 |--    |NC           |
|AC3  |--    |NC           |
|AD3  |--    |NC           |
|AC4  |--    |NC           |
|AD4  |--    |NC           |
|E3   |--    |NC           |
|E4   |--    |NC           |
|D3   |--    |NC           |
|D4   |--    |NC           |
+-----+------+-------------+------------+

+-----------------------------------------------------------------------------+
|Control Signals                                                              |
+-----------------------------------------------------------------------------+
+----+----------+-------+------------+------+--------------------+
|Name|Location  |Fan-Out|Usage       |Global|Global Resource Used|
+----+----------+-------+------------+------+--------------------+
|clk |Unassigned|2      |Clock       |no    |--                  |
|i~1 |Unassigned|1      |Clock enable|no    |--                  |
+----+----------+-------+------------+------+--------------------+

+-----------------------------------------------------------------------------+
|Non-Global High Fan-Out Signals                                              |
+-----------------------------------------------------------------------------+
+----------+-------+
|Name      |Fan-Out|
+----------+-------+
|odden~reg0|3      |
|hlmux     |2      |
|clk       |2      |
|i~1       |1      |
|hlmux1    |1      |
+----------+-------+

+-----------------------------------------------------------------------------+
|Timing Settings                                                              |
+-----------------------------------------------------------------------------+
+-----------------+-----------+----------------+----------------------------------------------------------------+------------------+
|Assignment File  |Source Name|Destination Name|Option                                                          |Setting           |
+-----------------+-----------+----------------+----------------------------------------------------------------+------------------+
|rader_hilbert.psf|Include external delays to/from device pins in fmax calculations|Off               |
|rader_hilbert.psf|Run All Timing Analyses                                         |Off               |
|rader_hilbert.psf|Ignore user-defined clock settings                              |Off               |
|rader_hilbert.psf|Default hold multicycle                                         |Same As Multicycle|
|rader_hilbert.psf|Cut off feedback from I/O pins                                  |On                |
|rader_hilbert.psf|Cut off clear and preset signal paths                           |On                |
|rader_hilbert.psf|Cut off read during write signal paths                          |On                |
|rader_hilbert.psf|Cut paths between unrelated clock domains                       |On                |
|rader_hilbert.psf|Number of paths to report                                       |200               |
|rader_hilbert.psf|Number of destination nodes to report                           |10                |
|rader_hilbert.psf|Number of source nodes to report per destination node           |10                |
|rader_hilbert.psf|Maximum Strongly Connected Component loop size                  |50                |
|Device name                                                     |EP1S25F780C5      |
+-----------------+-----------+----------------+----------------------------------------------------------------+------------------+

+-----------------------------------------------------------------------------+
|fmax (not incl. delays to/from pins)                                         |
+-----------------------------------------------------------------------------+
+-------------------------------+-------------+--------------------------------+
|Clock Name                     |Required fmax|Actual fmax (period)            |
|   -- Destination Register Name|             |                                |
|      -- Source Register Name  |             |                                |
+-------------------------------+-------------+--------------------------------+
|clk                            |None         |334.90 MHz ( period = 2.986 ns )|
|   -- odden~reg0               |None         |334.90 MHz ( period = 2.986 ns )|
|      -- hlmux1                |None         |334.90 MHz ( period = 2.986 ns )|
|      -- odden~reg0            |None         |Restricted to 422.12 MHz        |
+-------------------------------+-------------+--------------------------------+

+-----------------------------------------------------------------------------+
|Register-to-Register fmax                                                    |
+-----------------------------------------------------------------------------+
+--------------------+-------------------------+-----------------+----------------------+-------------+--------------------------------+
|Source Register Name|Destination Register Name|Source Clock Name|Destination Clock Name|Required fmax|Actual fmax (period)            |
+--------------------+-------------------------+-----------------+----------------------+-------------+--------------------------------+
|hlmux1              |odden~reg0               |clk              |clk                   |None         |334.90 MHz ( period = 2.986 ns )|
|odden~reg0          |odden~reg0               |clk              |clk                   |None         |Restricted to 422.12 MHz        |
+--------------------+-------------------------+-----------------+----------------------+-------------+--------------------------------+

+-----------------------------------------------------------------------------+
|tsu (Input Setup Times)                                                      |
+-----------------------------------------------------------------------------+
+-------------------+------------+----------+
|Data Pin Name      |Required tsu|Actual tsu|
|   -- Register Name|            |          |
|      -- Clock Name|            |          |
+-------------------+------------+----------+
|hlmux              |None        |1.616 ns  |
|   -- odden~reg0   |None        |1.616 ns  |
|      -- clk       |None        |1.616 ns  |
|   -- hlmux1       |None        |0.029 ns  |
|      -- clk       |None        |0.029 ns  |
+-------------------+------------+----------+

+-----------------------------------------------------------------------------+
|th (Input Hold Times)                                                        |
+-----------------------------------------------------------------------------+
+-------------------+-----------+---------+
|Data Pin Name      |Required th|Actual th|
|   -- Register Name|           |         |
|      -- Clock Name|           |         |
+-------------------+-----------+---------+
|hlmux              |None       |0.070 ns |
|   -- hlmux1       |None       |0.070 ns |
|      -- clk       |None       |0.070 ns |
|   -- odden~reg0   |None       |<= 0 ns  |
|      -- clk       |None       |<= 0 ns  |
+-------------------+-----------+---------+

+-----------------------------------------------------------------------------+
|tco (Clock to Output Delays)                                                 |
+-----------------------------------------------------------------------------+
+-------------------+------------+----------+
|Output Name        |Required tco|Actual tco|
|   -- Register Name|            |          |
|      -- Clock Name|            |          |
+-------------------+------------+----------+
|odden              |None        |7.137 ns  |
|   -- odden~reg0   |None        |7.137 ns  |
|      -- clk       |None        |7.137 ns  |
|evenen             |None        |7.137 ns  |
|   -- odden~reg0   |None        |7.137 ns  |
|      -- clk       |None        |7.137 ns  |
+-------------------+------------+----------+

+-----------------------------------------------------------------------------+
|Processing Time                                                              |
+-----------------------------------------------------------------------------+
+-----------------+------------+
|Module Name      |Elapsed Time|
+-----------------+------------+
|Database Builder |00:00:02    |
|Logic Synthesizer|00:00:09    |
|Delay Annotator  |00:00:24    |
|Timing Analyzer  |00:00:00    |
|Total            |00:00:35    |
+-----------------+------------+