oesel.csf.rpt

FPGA开发光盘各章节实例的设计工程与源码

oesel - Quartus II Compilation Report File
-------------------------------------------------------------------------------

+-------------------------------------------------------------------+
|Report Information                                                 |
+------------------+------------------------------------------------+
|Project           |e:\rader_hilbert\db\rader_hilbert.quartus_db    |
|Compiler Settings |oesel                                           |
|Quartus II Version|2.1 Build 189 09/05/2002 SP 1 SJ Full Version   |
+------------------+------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "oesel" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            Synthesis Section
                Post-Synthesis Resource Utilization by Entity
            Device Options
            Equations
            Resource Section
                Resource Usage Summary
                Input Pins
                Output Pins
                Delay Chain Summary
                All Package Pins
                Control Signals
                Non-Global High Fan-Out Signals
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tsu (Input Setup Times)
                th (Input Hold Times)
                tco (Clock to Output Delays)
            Processing Time

+-----------------------------------------------------------------------------+
|Legal Notice                                                                 |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
|General Settings                                                             |
+-----------------------------------------------------------------------------+
+-----------------+-------------------+
|Option           |Setting            |
+-----------------+-------------------+
|Start date & time|06/17/2003 10:05:20|
|Main task        |Compilation        |
|Settings name    |oesel              |
+-----------------+-------------------+

+-----------------------------------------------------------------------------+
|Summary                                                                      |
+-----------------------------------------------------------------------------+
+-----------------------------------+---------------------+
|Processing status                  |Fitting Unsuccessful |
|Timing requirements/analysis status|No requirements      |
|Chip name                          |oesel                |
|Device for compilation             |EP1S25F780C5         |
|Total logic elements               |3 / 25,660 ( < 1 % ) |
|Total pins                         |4 / 597 ( < 1 % )    |
|Total memory bits                  |0 / 1,944,576 ( 0 % )|
|DSP block 9-bit elements           |0 / 80 ( 0 % )       |
|PLLs                               |0 / 6 ( 0 % )        |
|Device for timing analysis         |EP1S25F780C5         |
+-----------------------------------+---------------------+

+-----------------------------------------------------------------------------+
|Compiler Settings                                                            |
+-----------------------------------------------------------------------------+
+------------------------------------------+------------------+
|Option                                    |Setting           |
+------------------------------------------+------------------+
|Chip name                                 |oesel             |
|Family name                               |Stratix           |
|Focus entity name                         ||oesel            |
|Device                                    |EP1S25F780C5      |
|Compilation mode                          |Full              |
|Disk space/compilation speed tradeoff     |Normal            |
|Preserve fewer node names                 |On                |
|Optimize timing                           |Normal Compilation|
|Optimize IOC register placement for timing|On                |
|Generate timing analyses                  |On                |
|Fast Fit compilation                      |Off               |
|SignalProbe compilation                   |Off               |
+------------------------------------------+------------------+

+-----------------------------------------------------------------------------+
|Messages                                                                     |
+-----------------------------------------------------------------------------+
Info: Found 2 design units and 1 entities in source file e:\rader_hilbert\oesel.vhd
  Info: Found design unit 1: oesel-behv
  Info: Found entity 1: oesel
Info: Found 1 design units and 1 entities in source file e:\rader_hilbert\indatamux.bdf
  Info: Found entity 1: indatamux
Info: Found 1 design units and 1 entities in source file e:\rader_hilbert\rader_hilbert.bdf
  Info: Found entity 1: rader_hilbert
Info: Found 2 design units and 1 entities in source file e:\rader_hilbert\contract.vhd
  Info: Found design unit 1: contract-behv
  Info: Found entity 1: contract
Info: Found 2 design units and 1 entities in source file e:\rader_hilbert\expand.vhd
  Info: Found design unit 1: expand-behv
  Info: Found entity 1: expand
Info: Found 2 design units and 1 entities in source file e:\rader_hilbert\sw1_4.vhd
  Info: Found design unit 1: sw1_4-behv
  Info: Found entity 1: sw1_4
Info: Duplicate registers merged to single register
  Info: Duplicate registers merged to single register evenen~reg0, power-up level has changed.
  Info: Duplicate registers merged to single register latchcnt
Info: Implemented 7 device resources
  Info: Implemented 2 input pins
  Info: Implemented 2 output pins
  Info: Implemented 3 logic cells
Info: Selected device EP1S25F780C5 for design oesel
Warning: Timing characteristics of device EP1S25F780C5 are preliminary
Info: Annotating netlist with estimated timing delays
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 334.9 MHz between source register hlmux1 and destination register odden~reg0 (period= 2.986 ns)
  Info: + Longest register to register delay is 2.818 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; REG Node = 'hlmux1'
    Info: 2: + IC(1.040 ns) + CELL(0.079 ns) = 1.119 ns; Loc. = Unassigned; COMB Node = 'i~1'
    Info: 3: + IC(1.040 ns) + CELL(0.659 ns) = 2.818 ns; Loc. = Unassigned; REG Node = 'odden~reg0'
    Info: Total cell delay = 0.738 ns
    Info: Total interconnect delay = 2.080 ns
  Info: - Smallest clock skew is 0.000 ns
    Info: + Shortest clock path from clock clk to destination register is 2.709 ns
      Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = Unassigned; CLK Node = 'clk'
      Info: 2: + IC(1.060 ns) + CELL(0.509 ns) = 2.709 ns; Loc. = Unassigned; REG Node = 'odden~reg0'
      Info: Total cell delay = 1.649 ns
      Info: Total interconnect delay = 1.060 ns
    Info: - Longest clock path from clock clk to source register is 2.709 ns
      Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = Unassigned; CLK Node = 'clk'
      Info: 2: + IC(1.060 ns) + CELL(0.509 ns) = 2.709 ns; Loc. = Unassigned; REG Node = 'hlmux1'
      Info: Total cell delay = 1.649 ns
      Info: Total interconnect delay = 1.060 ns
  Info: + Micro clock to output delay of source is 0.159 ns
  Info: + Micro setup delay of destination is 0.009 ns
Info: Design oesel: Netlist extraction and synthesis were successful. 0 errors, 2 warnings

+-----------------------------------------------------------------------------+
|Hierarchy                                                                    |
+-----------------------------------------------------------------------------+
CompileHierarchy
  oesel

+-----------------------------------------------------------------------------+
|Post-Synthesis Resource Utilization by Entity                                |
+-----------------------------------------------------------------------------+
+--------------------------+-----------+---------+-----------+------------+----+------------+-------------------+
|Compilation Hierarchy Node|Logic Cells|Registers|Memory Bits|DSP Elements|Pins|Virtual Pins|Full Hierarchy Name|
+--------------------------+-----------+---------+-----------+------------+----+------------+-------------------+
||oesel                    |3          |2        |0          |0           |4   |0           ||oesel             |
+--------------------------+-----------+---------+-----------+------------+----+------------+-------------------+

+-----------------------------------------------------------------------------+
|Device Options                                                               |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------+------------------------+
|Option                                                          |Setting                 |
+----------------------------------------------------------------+------------------------+
|Auto-restart configuration after error                          |Off                     |
|Release clears before tri-states                                |Off                     |
|Enable user-supplied start-up clock (CLKUSR)                    |Off                     |
|Enable device-wide reset (DEV_CLRn)                             |Off                     |
|Enable device-wide output enable (DEV_OE)                       |Off                     |
|Enable INIT_DONE output                                         |Off                     |
|Auto-increment JTAG user code for multiple configuration devices|On                      |
|Disable CONF_DONE and nSTATUS pull-ups on configuration device  |Off                     |
|Generate Tabular Text File (.ttf)                               |Off                     |
|Generate Raw Binary File (.rbf)                                 |Off                     |
|Generate Hexadecimal Output File (.hexout)                      |Off                     |
|Configuration scheme                                            |Passive Serial          |
|Hexadecimal Output File count direction                         |Up                      |
|Hexadecimal Output File start address                           |0                       |
|Reserve all unused pins                                         |As output driving ground|
|Configuration device                                            |EPC2                    |
|Base pin-out file on sameframe device                           |Off                     |
+----------------------------------------------------------------+------------------------+

+-----------------------------------------------------------------------------+
|Equations                                                                    |
+-----------------------------------------------------------------------------+
The equations can be found in e:\rader_hilbert\oesel.eqn.

+-----------------------------------------------------------------------------+
|Resource Usage Summary                                                       |
+-----------------------------------------------------------------------------+
+------------------------+---------------------+
|Resource                |Usage                |
+------------------------+---------------------+
|Logic cells             |3 / 25,660 ( < 1 % ) |
|Flipflops               |2 / 27,451 ( < 1 % ) |
|I/O pins                |4 / 597 ( < 1 % )    |
|Clock pins              |0                    |
|Dedicated input pins    |0                    |
|Global signals          |0                    |
|M512s                   |0 / 224 ( 0 % )      |
|M4Ks                    |0 / 138 ( 0 % )      |
|Mega RAMs               |0 / 2 ( 0 % )        |
|Total memory bits       |0 / 1,944,576 ( 0 % )|
|Total RAM block bits    |0 / 1,944,576 ( 0 % )|
|DSP block 9-bit elements|0 / 80 ( 0 % )       |
|PLLs                    |0 / 6 ( 0 % )        |
|Global clocks           |0 / 16 ( 0 % )       |
|Regional clocks         |0 / 16 ( 0 % )       |
|Fast regional clocks    |0 / 8 ( 0 % )        |
|DIFFIOCLKs              |0 / 16 ( 0 % )       |
|SERDES transmitters     |0 / 78 ( 0 % )       |
|SERDES receivers        |0 / 78 ( 0 % )       |
|Maximum fan-out node    |odden~reg0           |
|Maximum fan-out         |3                    |
|Total fan-out           |9                    |
|Average fan-out         |1.29                 |
+------------------------+---------------------+

+-----------------------------------------------------------------------------+
|Input Pins                                                                   |
+-----------------------------------------------------------------------------+
+-----+----------+---------------------+------------------+------+--------------+-------------+--------------+---------------+--------+------------+---------+------------+-----------+
|Name |Pin #     |Combinational Fan-Out|Registered Fan-Out|Global|Input Register|Power Up High|Slow Slew Rate|PCI I/O Enabled|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard|Termination|
+-----+----------+---------------------+------------------+------+--------------+-------------+--------------+---------------+--------+------------+---------+------------+-----------+
|clk  |Unassigned|2                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
|hlmux|Unassigned|2                    |0                 |no    |no            |no           |no            |no             |no      |Off         |no       |LVTTL       |Off        |
+-----+----------+---------------------+------------------+------+--------------+-------------+--------------+---------------+--------+------------+---------+------------+-----------+

+-----------------------------------------------------------------------------+
|Output Pins                                                                  |
+-----------------------------------------------------------------------------+
+------+----------+---------------+----------------------+-------------+--------------+---------------+----------+--------+------------+---------+------------+----------------+-----------+
|Name  |Pin #     |Output Register|Output Enable Register|Power Up High|Slow Slew Rate|PCI I/O Enabled|Open Drain|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard|Current Strength|Termination|
+------+----------+---------------+----------------------+-------------+--------------+---------------+----------+--------+------------+---------+------------+----------------+-----------+
|evenen|Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
|odden |Unassigned|no             |no                    |no           |no            |no             |no        |no      |Off         |no       |LVTTL       |Default         |Off        |
+------+----------+---------------+----------------------+-------------+--------------+---------------+----------+--------+------------+---------+------------+----------------+-----------+

+-----------------------------------------------------------------------------+
|Delay Chain Summary                                                          |
+-----------------------------------------------------------------------------+
+------+--------+-----------+---------------------+-----------------------+--------------------------------------+-------------------------------+------------------------------+---+----+--------------------------+
|Name  |Pin Type|Pad to Core|Pad to Input Register|Core to Output Register|Clock Enable to Output Enable Register|Clock Enable to Output Register|Clock Enable to Input Register|TCO|TCOE|Falling Edge Output Enable|
+------+--------+-----------+---------------------+-----------------------+--------------------------------------+-------------------------------+------------------------------+---+----+--------------------------+
|clk   |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|hlmux |Input   |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|odden |Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
|evenen|Output  |OFF        |OFF                  |OFF                    |OFF                                   |OFF                            |OFF                           |OFF|OFF |OFF                       |
+------+--------+-----------+---------------------+-----------------------+--------------------------------------+-------------------------------+------------------------------+---+----+--------------------------+

+-----------------------------------------------------------------------------+
|All Package Pins                                                             |
+-----------------------------------------------------------------------------+
+-----+------+-------------+------------+
|Pin #|Bank #|Usage        |I/O Standard|
+-----+------+-------------+------------+
|F24  |2     |GND*         |
|F23  |2     |GND*         |
|C27  |2     |GND*         |
|C28  |2     |GND*         |
|G23  |2     |GND*         |
|G24  |2     |GND*         |
|D27  |2     |GND*         |
|D28  |2     |GND*         |
|H24  |2     |GND*         |
|H23  |2     |GND*         |
|E27  |2     |GND*         |
|E28  |2     |GND*         |
|H22  |2     |GND*         |
|H21  |2     |GND*         |
|E24  |2     |GND          |
|F25  |2     |GND*         |
|F26  |2     |GND*         |
|J24  |2     |GND*         |