rader_hilbert.fit.summary

FPGA开发光盘各章节实例的设计工程与源码

Fitter Status : Successful - Mon Dec 10 15:26:00 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : rader_hilbert
Top-level Entity Name : rader_hilbert
Family : Stratix
Device : EP1S25F780C5
Timing Models : Final
Total logic elements : 296 / 25,660 ( 1 % )
Total pins : 51 / 598 ( 9 % )
Total virtual pins : 0
Total memory bits : 0 / 1,944,576 ( 0 % )
DSP block 9-bit elements : 4 / 80 ( 5 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )