sw1_4.vhd

FPGA开发光盘各章节实例的设计工程与源码

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity sw1_4 is 
  port(
	clk									   : in std_logic;
	ad_clk  						  	   : in  std_logic;
	indata								   : in  std_logic_vector(15 downto 0);
	outdata                                : out std_logic_vector(15 downto 0)
		);
end sw1_4;
architecture behv of sw1_4 is
	signal   temp	 : std_logic_vector(15 downto 0);
	signal   ad_clk1 : std_logic;
begin
process (clk)
	variable cnt	: integer range 0 to 3;--std_logic_vector(1 downto 0);
begin	
	if (clk'event and clk='1') then
		  ad_clk1<=ad_clk;
		if ((not ad_clk1) and ad_clk)='1' then
		 if cnt=0 then
		  temp<=indata;
		 else
		  temp<=temp;
		 end if;
		  cnt:=cnt+1;
	    end if;
		  outdata<=temp;
	end if;
end process;
end behv;