oesel.ssf

来自「FPGA开发光盘各章节实例的设计工程与源码」· SSF 代码 · 共 15 行

SIMULATOR_SETTINGS
{
	ESTIMATE_POWER_CONSUMPTION = OFF;
	GLITCH_INTERVAL = "1 ns";
	GLITCH_DETECTION = OFF;
	SIMULATION_COVERAGE = ON;
	CHECK_OUTPUTS = OFF;
	SETUP_HOLD_DETECTION = OFF;
	USE_COMPILER_SETTINGS = oesel;
	ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
	SIMULATION_MODE = TIMING;
	START_TIME = 0ns;
	POWER_ESTIMATION_START_TIME = "0 ns";
}