rader_hilbert.tan.rpt

FPGA开发光盘各章节实例的设计工程与源码

; Worst-case tco               ; N/A                                      ; None          ; 7.145 ns                         ; sw1_4:inst23|outdata[7]                                          ; Qn[7]                                                                                                            ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 1.771 ns                         ; xn[11]                                                           ; indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                ; --         ; clk      ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 6.513 ns                         ; sw1_4:inst26|outdata[6]                                          ; In[6]                                                                                                            ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 38.35 MHz ( period = 26.074 ns ) ; indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[16] ; clk        ; clk      ; 0            ;
; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; rd_contract:inst22|wconout[5]                                    ; rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[5]                                                               ; clk        ; clk      ; 32           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                  ;                                                                                                                  ;            ;          ; 32           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S25F780C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                              ; To                                                                                                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;