generator_and2.vhd

FPGA开发光盘各章节实例的设计工程与源码

--与门模块generator_and2.vhd文件
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-- DESCRIPTION   :  Gate: AND
-- 
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library IEEE;
use IEEE.std_logic_1164.all;

entity generator_and2 is
	port (
		I0 : in STD_LOGIC;
		I1 : in STD_LOGIC;
		O : out STD_LOGIC
	);
end entity;

architecture and_anGen_arch of generator_and2 is
begin
	O <= I0 and I1;
end architecture and_anGen_arch;