generator.hier_info

FPGA开发光盘各章节实例的设计工程与源码

|generator
CLK => generator_reg8:U7.CLK
CLK => generator_acc6:U4.CLK
CLK => generator_reg6:U2.CLK
CLK => generator_reg6:U1.CLK
DATA[0] => generator_reg6:U2.DATA[0]
DATA[0] => generator_reg6:U1.DATA[0]
DATA[1] => generator_reg6:U2.DATA[1]
DATA[1] => generator_reg6:U1.DATA[1]
DATA[2] => generator_reg6:U2.DATA[2]
DATA[2] => generator_reg6:U1.DATA[2]
DATA[3] => generator_reg6:U2.DATA[3]
DATA[3] => generator_reg6:U1.DATA[3]
DATA[4] => generator_reg6:U2.DATA[4]
DATA[4] => generator_reg6:U1.DATA[4]
DATA[5] => generator_reg6:U2.DATA[5]
DATA[5] => generator_reg6:U1.DATA[5]
PR => generator_and2:U9.I1
FR => generator_and2:U8.I1
CLR => generator_reg8:U7.CLR
CLR => generator_acc6:U4.CLR
CLR => generator_reg6:U2.CLR
CLR => generator_reg6:U1.CLR
CE => generator_and2:U9.I0
CE => generator_and2:U8.I0
CE => generator_reg8:U7.CE
CE => generator_acc6:U4.CE
Q[0] <= generator_reg8:U7.Q[0]
Q[1] <= generator_reg8:U7.Q[1]
Q[2] <= generator_reg8:U7.Q[2]
Q[3] <= generator_reg8:U7.Q[3]
Q[4] <= generator_reg8:U7.Q[4]
Q[5] <= generator_reg8:U7.Q[5]
Q[6] <= generator_reg8:U7.Q[6]
Q[7] <= generator_reg8:U7.Q[7]


|generator|generator_reg6:U1
CLR => TEMP_Q_0[0].ACLR
CLR => TEMP_Q_0[1].ACLR
CLR => TEMP_Q_0[2].ACLR
CLR => TEMP_Q_0[3].ACLR
CLR => TEMP_Q_0[4].ACLR
CLR => TEMP_Q_0[5].ACLR
CE => TEMP_Q_0[0].ENA
CE => TEMP_Q_0[1].ENA
CE => TEMP_Q_0[2].ENA
CE => TEMP_Q_0[3].ENA
CE => TEMP_Q_0[4].ENA
CE => TEMP_Q_0[5].ENA
CLK => TEMP_Q_0[0].CLK
CLK => TEMP_Q_0[1].CLK
CLK => TEMP_Q_0[2].CLK
CLK => TEMP_Q_0[3].CLK
CLK => TEMP_Q_0[4].CLK
CLK => TEMP_Q_0[5].CLK
DATA[0] => TEMP_Q_0[0].DATAIN
DATA[1] => TEMP_Q_0[1].DATAIN
DATA[2] => TEMP_Q_0[2].DATAIN
DATA[3] => TEMP_Q_0[3].DATAIN
DATA[4] => TEMP_Q_0[4].DATAIN
DATA[5] => TEMP_Q_0[5].DATAIN
Q[0] <= TEMP_Q_0[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_0[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_0[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_0[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_0[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_0[5].DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_sin:U6
OE => comb~0.OE
OE => comb~1.OE
OE => comb~2.OE
OE => comb~3.OE
OE => comb~4.OE
OE => comb~5.OE
OE => comb~6.OE
OE => comb~7.OE
ADDRESS[0] => Mux0.IN69
ADDRESS[0] => Mux1.IN69
ADDRESS[0] => Mux2.IN69
ADDRESS[0] => Mux3.IN69
ADDRESS[0] => Mux4.IN69
ADDRESS[0] => Mux5.IN69
ADDRESS[0] => Mux6.IN69
ADDRESS[0] => Mux7.IN69
ADDRESS[1] => Mux0.IN68
ADDRESS[1] => Mux1.IN68
ADDRESS[1] => Mux2.IN68
ADDRESS[1] => Mux3.IN68
ADDRESS[1] => Mux4.IN68
ADDRESS[1] => Mux5.IN68
ADDRESS[1] => Mux6.IN68
ADDRESS[1] => Mux7.IN68
ADDRESS[2] => Mux0.IN67
ADDRESS[2] => Mux1.IN67
ADDRESS[2] => Mux2.IN67
ADDRESS[2] => Mux3.IN67
ADDRESS[2] => Mux4.IN67
ADDRESS[2] => Mux5.IN67
ADDRESS[2] => Mux6.IN67
ADDRESS[2] => Mux7.IN67
ADDRESS[3] => Mux0.IN66
ADDRESS[3] => Mux1.IN66
ADDRESS[3] => Mux2.IN66
ADDRESS[3] => Mux3.IN66
ADDRESS[3] => Mux4.IN66
ADDRESS[3] => Mux5.IN66
ADDRESS[3] => Mux6.IN66
ADDRESS[3] => Mux7.IN66
ADDRESS[4] => Mux0.IN65
ADDRESS[4] => Mux1.IN65
ADDRESS[4] => Mux2.IN65
ADDRESS[4] => Mux3.IN65
ADDRESS[4] => Mux4.IN65
ADDRESS[4] => Mux5.IN65
ADDRESS[4] => Mux6.IN65
ADDRESS[4] => Mux7.IN65
ADDRESS[5] => Mux0.IN64
ADDRESS[5] => Mux1.IN64
ADDRESS[5] => Mux2.IN64
ADDRESS[5] => Mux3.IN64
ADDRESS[5] => Mux4.IN64
ADDRESS[5] => Mux5.IN64
ADDRESS[5] => Mux6.IN64
ADDRESS[5] => Mux7.IN64
Q[0] <= comb~0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= comb~1.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= comb~2.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= comb~3.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= comb~4.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= comb~5.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= comb~6.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= comb~7.DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_reg6:U2
CLR => TEMP_Q_0[0].ACLR
CLR => TEMP_Q_0[1].ACLR
CLR => TEMP_Q_0[2].ACLR
CLR => TEMP_Q_0[3].ACLR
CLR => TEMP_Q_0[4].ACLR
CLR => TEMP_Q_0[5].ACLR
CE => TEMP_Q_0[0].ENA
CE => TEMP_Q_0[1].ENA
CE => TEMP_Q_0[2].ENA
CE => TEMP_Q_0[3].ENA
CE => TEMP_Q_0[4].ENA
CE => TEMP_Q_0[5].ENA
CLK => TEMP_Q_0[0].CLK
CLK => TEMP_Q_0[1].CLK
CLK => TEMP_Q_0[2].CLK
CLK => TEMP_Q_0[3].CLK
CLK => TEMP_Q_0[4].CLK
CLK => TEMP_Q_0[5].CLK
DATA[0] => TEMP_Q_0[0].DATAIN
DATA[1] => TEMP_Q_0[1].DATAIN
DATA[2] => TEMP_Q_0[2].DATAIN
DATA[3] => TEMP_Q_0[3].DATAIN
DATA[4] => TEMP_Q_0[4].DATAIN
DATA[5] => TEMP_Q_0[5].DATAIN
Q[0] <= TEMP_Q_0[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_0[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_0[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_0[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_0[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_0[5].DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_adder:U3
A[0] => Add0.IN6
A[1] => Add0.IN5
A[2] => Add0.IN4
A[3] => Add0.IN3
A[4] => Add0.IN2
A[5] => Add0.IN1
B[0] => Add0.IN12
B[1] => Add0.IN11
B[2] => Add0.IN10
B[3] => Add0.IN9
B[4] => Add0.IN8
B[5] => Add0.IN7
Q[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_acc6:U4
A[0] => Add0.IN12
A[1] => Add0.IN11
A[2] => Add0.IN10
A[3] => Add0.IN9
A[4] => Add0.IN8
A[5] => Add0.IN7
CE => Q~0.OUTPUTSELECT
CE => Q~1.OUTPUTSELECT
CE => Q~2.OUTPUTSELECT
CE => Q~3.OUTPUTSELECT
CE => Q~4.OUTPUTSELECT
CE => Q~5.OUTPUTSELECT
CLK => Q[0]~reg0.CLK
CLK => Q[1]~reg0.CLK
CLK => Q[2]~reg0.CLK
CLK => Q[3]~reg0.CLK
CLK => Q[4]~reg0.CLK
CLK => Q[5]~reg0.CLK
CLR => Q~6.OUTPUTSELECT
CLR => Q~7.OUTPUTSELECT
CLR => Q~8.OUTPUTSELECT
CLR => Q~9.OUTPUTSELECT
CLR => Q~10.OUTPUTSELECT
CLR => Q~11.OUTPUTSELECT
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_reg8:U7
CLR => TEMP_Q_1[0].ACLR
CLR => TEMP_Q_1[1].ACLR
CLR => TEMP_Q_1[2].ACLR
CLR => TEMP_Q_1[3].ACLR
CLR => TEMP_Q_1[4].ACLR
CLR => TEMP_Q_1[5].ACLR
CLR => TEMP_Q_1[6].ACLR
CLR => TEMP_Q_1[7].ACLR
CE => TEMP_Q_1[0].ENA
CE => TEMP_Q_1[1].ENA
CE => TEMP_Q_1[2].ENA
CE => TEMP_Q_1[3].ENA
CE => TEMP_Q_1[4].ENA
CE => TEMP_Q_1[5].ENA
CE => TEMP_Q_1[6].ENA
CE => TEMP_Q_1[7].ENA
CLK => TEMP_Q_1[0].CLK
CLK => TEMP_Q_1[1].CLK
CLK => TEMP_Q_1[2].CLK
CLK => TEMP_Q_1[3].CLK
CLK => TEMP_Q_1[4].CLK
CLK => TEMP_Q_1[5].CLK
CLK => TEMP_Q_1[6].CLK
CLK => TEMP_Q_1[7].CLK
DATA[0] => TEMP_Q_1[0].DATAIN
DATA[1] => TEMP_Q_1[1].DATAIN
DATA[2] => TEMP_Q_1[2].DATAIN
DATA[3] => TEMP_Q_1[3].DATAIN
DATA[4] => TEMP_Q_1[4].DATAIN
DATA[5] => TEMP_Q_1[5].DATAIN
DATA[6] => TEMP_Q_1[6].DATAIN
DATA[7] => TEMP_Q_1[7].DATAIN
Q[0] <= TEMP_Q_1[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_1[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_1[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_1[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_1[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_1[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP_Q_1[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP_Q_1[7].DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_and2:U8
I0 => O~0.IN0
I1 => O~0.IN1
O <= O~0.DB_MAX_OUTPUT_PORT_TYPE


|generator|generator_and2:U9
I0 => O~0.IN0
I1 => O~0.IN1
O <= O~0.DB_MAX_OUTPUT_PORT_TYPE