generator.fit.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.108 ns register register " "Info: Estimated most critical path is register to register delay of 4.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_acc6:U4\|Q\[0\] 1 REG LAB_X9_Y17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y17; Fanout = 3; REG Node = 'generator_acc6:U4\|Q\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { generator_acc6:U4|Q[0] } "NODE_NAME" } } { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.443 ns) 0.954 ns generator_adder:U3\|Q\[0\]~40 2 COMB LAB_X8_Y17 2 " "Info: 2: + IC(0.511 ns) + CELL(0.443 ns) = 0.954 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[0\]~40'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.954 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 1.012 ns generator_adder:U3\|Q\[1\]~34 3 COMB LAB_X8_Y17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 1.012 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[1\]~34'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { generator_adder:U3|Q[0]~40 generator_adder:U3|Q[1]~34 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 1.070 ns generator_adder:U3\|Q\[2\]~38 4 COMB LAB_X8_Y17 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 1.070 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[2\]~38'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { generator_adder:U3|Q[1]~34 generator_adder:U3|Q[2]~38 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 1.284 ns generator_adder:U3\|Q\[3\]~42 5 COMB LAB_X8_Y17 2 " "Info: 5: + IC(0.000 ns) + CELL(0.214 ns) = 1.284 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[3\]~42'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.214 ns" { generator_adder:U3|Q[2]~38 generator_adder:U3|Q[3]~42 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.469 ns) 1.753 ns generator_adder:U3\|Q\[5\]~35 6 COMB LAB_X8_Y17 24 " "Info: 6: + IC(0.000 ns) + CELL(0.469 ns) = 1.753 ns; Loc. = LAB_X8_Y17; Fanout = 24; COMB Node = 'generator_adder:U3\|Q\[5\]~35'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.469 ns" { generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.183 ns) 2.839 ns generator_sin:U6\|Mux1~163 7 COMB LAB_X8_Y18 1 " "Info: 7: + IC(0.903 ns) + CELL(0.183 ns) = 2.839 ns; Loc. = LAB_X8_Y18; Fanout = 1; COMB Node = 'generator_sin:U6\|Mux1~163'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.086 ns" { generator_adder:U3|Q[5]~35 generator_sin:U6|Mux1~163 } "NODE_NAME" } } { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.075 ns) 3.307 ns generator_sin:U6\|Mux1~164 8 COMB LAB_X8_Y18 1 " "Info: 8: + IC(0.393 ns) + CELL(0.075 ns) = 3.307 ns; Loc. = LAB_X8_Y18; Fanout = 1; COMB Node = 'generator_sin:U6\|Mux1~164'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { generator_sin:U6|Mux1~163 generator_sin:U6|Mux1~164 } "NODE_NAME" } } { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.458 ns) 4.108 ns generator_reg8:U7\|TEMP_Q_1\[6\] 9 REG LAB_X7_Y18 1 " "Info: 9: + IC(0.343 ns) + CELL(0.458 ns) = 4.108 ns; Loc. = LAB_X7_Y18; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.801 ns" { generator_sin:U6|Mux1~164 generator_reg8:U7|TEMP_Q_1[6] } "NODE_NAME" } } { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.958 ns ( 47.66 % ) " "Info: Total cell delay = 1.958 ns ( 47.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.150 ns ( 52.34 % ) " "Info: Total interconnect delay = 2.150 ns ( 52.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.108 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40 generator_adder:U3|Q[1]~34 generator_adder:U3|Q[2]~38 generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 generator_sin:U6|Mux1~163 generator_sin:U6|Mux1~164 generator_reg8:U7|TEMP_Q_1[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y10 X9_Y20 " "Info: The peak interconnect region extends from location X0_Y10 to location X9_Y20" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "203 " "Info: Allocated 203 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 11:56:50 2007 " "Info: Processing ended: Mon Dec 10 11:56:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.fit.smsg " "Info: Generated suppressed messages file F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}