generator.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register generator_acc6:U4\|Q\[0\] register generator_reg8:U7\|TEMP_Q_1\[0\] 230.31 MHz 4.342 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 230.31 MHz between source register \"generator_acc6:U4\|Q\[0\]\" and destination register \"generator_reg8:U7\|TEMP_Q_1\[0\]\" (period= 4.342 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.177 ns + Longest register register " "Info: + Longest register to register delay is 4.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_acc6:U4\|Q\[0\] 1 REG LC_X9_Y17_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y17_N1; Fanout = 3; REG Node = 'generator_acc6:U4\|Q\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { generator_acc6:U4|Q[0] } "NODE_NAME" } } { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.451 ns) 0.993 ns generator_adder:U3\|Q\[0\]~40COUT1 2 COMB LC_X8_Y17_N1 2 " "Info: 2: + IC(0.542 ns) + CELL(0.451 ns) = 0.993 ns; Loc. = LC_X8_Y17_N1; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[0\]~40COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40COUT1 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.053 ns generator_adder:U3\|Q\[1\]~34COUT1 3 COMB LC_X8_Y17_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 1.053 ns; Loc. = LC_X8_Y17_N2; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[1\]~34COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { generator_adder:U3|Q[0]~40COUT1 generator_adder:U3|Q[1]~34COUT1 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.113 ns generator_adder:U3\|Q\[2\]~38COUT1 4 COMB LC_X8_Y17_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 1.113 ns; Loc. = LC_X8_Y17_N3; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[2\]~38COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { generator_adder:U3|Q[1]~34COUT1 generator_adder:U3|Q[2]~38COUT1 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.118 ns) 1.231 ns generator_adder:U3\|Q\[3\]~42 5 COMB LC_X8_Y17_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.118 ns) = 1.231 ns; Loc. = LC_X8_Y17_N4; Fanout = 2; COMB Node = 'generator_adder:U3\|Q\[3\]~42'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { generator_adder:U3|Q[2]~38COUT1 generator_adder:U3|Q[3]~42 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 1.680 ns generator_adder:U3\|Q\[5\]~35 6 COMB LC_X8_Y17_N6 24 " "Info: 6: + IC(0.000 ns) + CELL(0.449 ns) = 1.680 ns; Loc. = LC_X8_Y17_N6; Fanout = 24; COMB Node = 'generator_adder:U3\|Q\[5\]~35'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 } "NODE_NAME" } } { "generator_adder.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_adder.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.127 ns) + CELL(0.183 ns) 2.990 ns generator_sin:U6\|Mux7~151 7 COMB LC_X7_Y18_N1 2 " "Info: 7: + IC(1.127 ns) + CELL(0.183 ns) = 2.990 ns; Loc. = LC_X7_Y18_N1; Fanout = 2; COMB Node = 'generator_sin:U6\|Mux7~151'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.310 ns" { generator_adder:U3|Q[5]~35 generator_sin:U6|Mux7~151 } "NODE_NAME" } } { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.183 ns) 3.517 ns generator_sin:U6\|Mux7~152 8 COMB LC_X7_Y18_N5 1 " "Info: 8: + IC(0.344 ns) + CELL(0.183 ns) = 3.517 ns; Loc. = LC_X7_Y18_N5; Fanout = 1; COMB Node = 'generator_sin:U6\|Mux7~152'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.527 ns" { generator_sin:U6|Mux7~151 generator_sin:U6|Mux7~152 } "NODE_NAME" } } { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.341 ns) + CELL(0.319 ns) 4.177 ns generator_reg8:U7\|TEMP_Q_1\[0\] 9 REG LC_X7_Y18_N0 1 " "Info: 9: + IC(0.341 ns) + CELL(0.319 ns) = 4.177 ns; Loc. = LC_X7_Y18_N0; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.660 ns" { generator_sin:U6|Mux7~152 generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.823 ns ( 43.64 % ) " "Info: Total cell delay = 1.823 ns ( 43.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.354 ns ( 56.36 % ) " "Info: Total interconnect delay = 2.354 ns ( 56.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.177 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40COUT1 generator_adder:U3|Q[1]~34COUT1 generator_adder:U3|Q[2]~38COUT1 generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 generator_sin:U6|Mux7~151 generator_sin:U6|Mux7~152 generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.177 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40COUT1 generator_adder:U3|Q[1]~34COUT1 generator_adder:U3|Q[2]~38COUT1 generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 generator_sin:U6|Mux7~151 generator_sin:U6|Mux7~152 generator_reg8:U7|TEMP_Q_1[0] } { 0.000ns 0.542ns 0.000ns 0.000ns 0.000ns 0.000ns 1.127ns 0.344ns 0.341ns } { 0.000ns 0.451ns 0.060ns 0.060ns 0.118ns 0.449ns 0.183ns 0.183ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.061 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_R25 26 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.542 ns) 3.061 ns generator_reg8:U7\|TEMP_Q_1\[0\] 2 REG LC_X7_Y18_N0 1 " "Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X7_Y18_N0; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.233 ns" { CLK generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.76 % ) " "Info: Total cell delay = 1.370 ns ( 44.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns ( 55.24 % ) " "Info: Total interconnect delay = 1.691 ns ( 55.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[0] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.060 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.060 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_R25 26 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.542 ns) 3.060 ns generator_acc6:U4\|Q\[0\] 2 REG LC_X9_Y17_N1 3 " "Info: 2: + IC(1.690 ns) + CELL(0.542 ns) = 3.060 ns; Loc. = LC_X9_Y17_N1; Fanout = 3; REG Node = 'generator_acc6:U4\|Q\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { CLK generator_acc6:U4|Q[0] } "NODE_NAME" } } { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.77 % ) " "Info: Total cell delay = 1.370 ns ( 44.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.690 ns ( 55.23 % ) " "Info: Total interconnect delay = 1.690 ns ( 55.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_acc6:U4|Q[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_acc6:U4|Q[0] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[0] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_acc6:U4|Q[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_acc6:U4|Q[0] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.177 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40COUT1 generator_adder:U3|Q[1]~34COUT1 generator_adder:U3|Q[2]~38COUT1 generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 generator_sin:U6|Mux7~151 generator_sin:U6|Mux7~152 generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.177 ns" { generator_acc6:U4|Q[0] generator_adder:U3|Q[0]~40COUT1 generator_adder:U3|Q[1]~34COUT1 generator_adder:U3|Q[2]~38COUT1 generator_adder:U3|Q[3]~42 generator_adder:U3|Q[5]~35 generator_sin:U6|Mux7~151 generator_sin:U6|Mux7~152 generator_reg8:U7|TEMP_Q_1[0] } { 0.000ns 0.542ns 0.000ns 0.000ns 0.000ns 0.000ns 1.127ns 0.344ns 0.341ns } { 0.000ns 0.451ns 0.060ns 0.060ns 0.118ns 0.449ns 0.183ns 0.183ns 0.319ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK generator_reg8:U7|TEMP_Q_1[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[0] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_acc6:U4|Q[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_acc6:U4|Q[0] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "generator_reg6:U2\|TEMP_Q_0\[1\] CE CLK 4.439 ns register " "Info: tsu for register \"generator_reg6:U2\|TEMP_Q_0\[1\]\" (data pin = \"CE\", clock pin = \"CLK\") is 4.439 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.489 ns + Longest pin register " "Info: + Longest pin to register delay is 7.489 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns CE 1 PIN PIN_C21 11 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C21; Fanout = 11; PIN Node = 'CE'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CE } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.154 ns) + CELL(0.366 ns) 5.607 ns generator_and2:U8\|O 2 COMB LC_X7_Y19_N2 6 " "Info: 2: + IC(4.154 ns) + CELL(0.366 ns) = 5.607 ns; Loc. = LC_X7_Y19_N2; Fanout = 6; COMB Node = 'generator_and2:U8\|O'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.520 ns" { CE generator_and2:U8|O } "NODE_NAME" } } { "generator_and2.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_and2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.705 ns) 7.489 ns generator_reg6:U2\|TEMP_Q_0\[1\] 3 REG LC_X9_Y17_N7 3 " "Info: 3: + IC(1.177 ns) + CELL(0.705 ns) = 7.489 ns; Loc. = LC_X9_Y17_N7; Fanout = 3; REG Node = 'generator_reg6:U2\|TEMP_Q_0\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.882 ns" { generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[1] } "NODE_NAME" } } { "generator_reg6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg6.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 28.82 % ) " "Info: Total cell delay = 2.158 ns ( 28.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.331 ns ( 71.18 % ) " "Info: Total interconnect delay = 5.331 ns ( 71.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.489 ns" { CE generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.489 ns" { CE CE~out0 generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[1] } { 0.000ns 0.000ns 4.154ns 1.177ns } { 0.000ns 1.087ns 0.366ns 0.705ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "generator_reg6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg6.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.060 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.060 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_R25 26 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.542 ns) 3.060 ns generator_reg6:U2\|TEMP_Q_0\[1\] 2 REG LC_X9_Y17_N7 3 " "Info: 2: + IC(1.690 ns) + CELL(0.542 ns) = 3.060 ns; Loc. = LC_X9_Y17_N7; Fanout = 3; REG Node = 'generator_reg6:U2\|TEMP_Q_0\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { CLK generator_reg6:U2|TEMP_Q_0[1] } "NODE_NAME" } } { "generator_reg6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg6.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.77 % ) " "Info: Total cell delay = 1.370 ns ( 44.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.690 ns ( 55.23 % ) " "Info: Total interconnect delay = 1.690 ns ( 55.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_reg6:U2|TEMP_Q_0[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_reg6:U2|TEMP_Q_0[1] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.489 ns" { CE generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.489 ns" { CE CE~out0 generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[1] } { 0.000ns 0.000ns 4.154ns 1.177ns } { 0.000ns 1.087ns 0.366ns 0.705ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_reg6:U2|TEMP_Q_0[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_reg6:U2|TEMP_Q_0[1] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[1\] generator_reg8:U7\|TEMP_Q_1\[1\] 7.349 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[1\]\" through register \"generator_reg8:U7\|TEMP_Q_1\[1\]\" is 7.349 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.061 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_R25 26 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.542 ns) 3.061 ns generator_reg8:U7\|TEMP_Q_1\[1\] 2 REG LC_X7_Y18_N8 1 " "Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X7_Y18_N8; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.233 ns" { CLK generator_reg8:U7|TEMP_Q_1[1] } "NODE_NAME" } } { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.76 % ) " "Info: Total cell delay = 1.370 ns ( 44.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns ( 55.24 % ) " "Info: Total interconnect delay = 1.691 ns ( 55.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK generator_reg8:U7|TEMP_Q_1[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[1] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.132 ns + Longest register pin " "Info: + Longest register to pin delay is 4.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_reg8:U7\|TEMP_Q_1\[1\] 1 REG LC_X7_Y18_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y18_N8; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { generator_reg8:U7|TEMP_Q_1[1] } "NODE_NAME" } } { "generator_reg8.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_reg8.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.756 ns) + CELL(2.376 ns) 4.132 ns Q\[1\] 2 PIN PIN_N22 0 " "Info: 2: + IC(1.756 ns) + CELL(2.376 ns) = 4.132 ns; Loc. = PIN_N22; Fanout = 0; PIN Node = 'Q\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.132 ns" { generator_reg8:U7|TEMP_Q_1[1] Q[1] } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 57.50 % ) " "Info: Total cell delay = 2.376 ns ( 57.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.756 ns ( 42.50 % ) " "Info: Total interconnect delay = 1.756 ns ( 42.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.132 ns" { generator_reg8:U7|TEMP_Q_1[1] Q[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.132 ns" { generator_reg8:U7|TEMP_Q_1[1] Q[1] } { 0.000ns 1.756ns } { 0.000ns 2.376ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK generator_reg8:U7|TEMP_Q_1[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[1] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.132 ns" { generator_reg8:U7|TEMP_Q_1[1] Q[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.132 ns" { generator_reg8:U7|TEMP_Q_1[1] Q[1] } { 0.000ns 1.756ns } { 0.000ns 2.376ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "generator_acc6:U4\|Q\[4\] CLR CLK -0.436 ns register " "Info: th for register \"generator_acc6:U4\|Q\[4\]\" (data pin = \"CLR\", clock pin = \"CLK\") is -0.436 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.060 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.060 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_R25 26 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.542 ns) 3.060 ns generator_acc6:U4\|Q\[4\] 2 REG LC_X9_Y17_N5 3 " "Info: 2: + IC(1.690 ns) + CELL(0.542 ns) = 3.060 ns; Loc. = LC_X9_Y17_N5; Fanout = 3; REG Node = 'generator_acc6:U4\|Q\[4\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { CLK generator_acc6:U4|Q[4] } "NODE_NAME" } } { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.77 % ) " "Info: Total cell delay = 1.370 ns ( 44.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.690 ns ( 55.23 % ) " "Info: Total interconnect delay = 1.690 ns ( 55.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_acc6:U4|Q[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_acc6:U4|Q[4] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.596 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLR 1 PIN PIN_R27 27 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_R27; Fanout = 27; PIN Node = 'CLR'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "generator.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.110 ns) + CELL(0.761 ns) 3.596 ns generator_acc6:U4\|Q\[4\] 2 REG LC_X9_Y17_N5 3 " "Info: 2: + IC(2.110 ns) + CELL(0.761 ns) = 3.596 ns; Loc. = LC_X9_Y17_N5; Fanout = 3; REG Node = 'generator_acc6:U4\|Q\[4\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { CLR generator_acc6:U4|Q[4] } "NODE_NAME" } } { "generator_acc6.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_acc6.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.486 ns ( 41.32 % ) " "Info: Total cell delay = 1.486 ns ( 41.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.110 ns ( 58.68 % ) " "Info: Total interconnect delay = 2.110 ns ( 58.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.596 ns" { CLR generator_acc6:U4|Q[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.596 ns" { CLR CLR~out0 generator_acc6:U4|Q[4] } { 0.000ns 0.000ns 2.110ns } { 0.000ns 0.725ns 0.761ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { CLK generator_acc6:U4|Q[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.060 ns" { CLK CLK~out0 generator_acc6:U4|Q[4] } { 0.000ns 0.000ns 1.690ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.596 ns" { CLR generator_acc6:U4|Q[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.596 ns" { CLR CLR~out0 generator_acc6:U4|Q[4] } { 0.000ns 0.000ns 2.110ns } { 0.000ns 0.725ns 0.761ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}