generator.map.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_reg6 generator_reg6:U1 " "Info: Elaborating entity \"generator_reg6\" for hierarchy \"generator_reg6:U1\"" {  } { { "generator.vhd" "U1" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 109 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_sin generator_sin:U6 " "Info: Elaborating entity \"generator_sin\" for hierarchy \"generator_sin:U6\"" {  } { { "generator.vhd" "U6" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 117 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_adder generator_adder:U3 " "Info: Elaborating entity \"generator_adder\" for hierarchy \"generator_adder:U3\"" {  } { { "generator.vhd" "U3" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 132 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_acc6 generator_acc6:U4 " "Info: Elaborating entity \"generator_acc6\" for hierarchy \"generator_acc6:U4\"" {  } { { "generator.vhd" "U4" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 138 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_reg8 generator_reg8:U7 " "Info: Elaborating entity \"generator_reg8\" for hierarchy \"generator_reg8:U7\"" {  } { { "generator.vhd" "U7" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 146 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_and2 generator_and2:U8 " "Info: Elaborating entity \"generator_and2\" for hierarchy \"generator_and2:U8\"" {  } { { "generator.vhd" "U8" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator.vhd" 154 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[0\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[0\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[1\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[1\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[2\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[2\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[3\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[3\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[4\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[4\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[5\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[5\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[6\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[6\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[7\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[7\]\" that feeds logic to a wire" {  } { { "generator_sin.vhd" "" { Text "F:/old_pc_p36n/old_F/xudong/mybook/07tijiao/程序及软件/cht05/s05p04p01/generator_sin.vhd" 19 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 11:56:31 2007 " "Info: Processing ended: Mon Dec 10 11:56:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IQSYN_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 0 "*******************************************************************" 0 0}
{ "Info" "IQSYN_START_BANNER_PRODUCT" "Partition Merge Quartus II " "Info: Running Quartus II Partition Merge" { { "Info" "IQSYN_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQSYN_START_BANNER_TIME" "Mon Dec 10 11:56:31 2007 " "Info: Processing started: Mon Dec 10 11:56:31 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 0 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "80 " "Info: Implemented 80 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "61 " "Info: Implemented 61 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQSYN_ERROR_COUNT" "Partition Merge 0 s 0 s Quartus II " "Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings" { { "Info" "IQSYN_END_BANNER_TIME" "Mon Dec 10 11:56:31 2007 " "Info: Processing ended: Mon Dec 10 11:56:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQSYN_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}