generator.vhd

FPGA开发光盘各章节实例的设计工程与源码

--顶层文件generator.vhd文件：

----------------------------------------------------------------------------------
--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is stored in a separate memory block.
-- NOTE: At least two samples per the highest output signal frequency are required
-- to produce -- a valid waveform.
-- The contents of the ROM is synchronously sent to the output in accordance with 
-- the selected frequency and phase shift. 
-- The following table shows how to configure the phase shift and signal frequency.
--
-- PR    FR     DATA Description 
-- 1      0   programming phase shift 
-- 0      1   programming work frequency 
-- 
--
-- FR: Specifies how many CLK cycles per a single analog waveform sample are required. 
-----------------------------------------------------------------------------------

------------------------------------------------------------------------------------
-- DESCRIPTION   :  Name : Analog Generator
-- 
------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator is
	port (
			CLK 	: in std_logic;
			DATA 	: in std_logic_vector(5 downto 0);
			PR 		: in std_logic;
			FR 		: in std_logic;
			CLR 	: in std_logic;
			CE 		: in std_logic;
			Q 		: out std_logic_vector(7 downto 0)
		);
end generator;

architecture generator_arch of generator is 

component generator_acc6
    port(
      A : in STD_LOGIC_VECTOR(5 downto 0);
      CE : in STD_LOGIC;
      CLK : in STD_LOGIC;
      CLR : in STD_LOGIC;
      Q : out STD_LOGIC_VECTOR(5 downto 0));
end component;

component generator_adder
    port (
      A : in STD_LOGIC_VECTOR(5 downto 0);
      B : in STD_LOGIC_VECTOR(5 downto 0);
      Q : out STD_LOGIC_VECTOR(5 downto 0));
end component;

component generator_and2
    port (
      I0 : in STD_LOGIC;
      I1 : in STD_LOGIC;
      O : out STD_LOGIC
);
end component;

component generator_sin
    port (
      OE : in STD_LOGIC;
      ADDRESS : in STD_LOGIC_VECTOR(5 downto 0);
      Q : out STD_LOGIC_VECTOR(7 downto 0) );
end component;

component generator_reg6
    port (
      CE : in STD_LOGIC;
      CLK : in STD_LOGIC;
      CLR : in STD_LOGIC;
      DATA : in STD_LOGIC_VECTOR(5 downto 0);
      Q : out STD_LOGIC_VECTOR(5 downto 0));
end component;

component generator_reg8
    port (
      CE : in STD_LOGIC;
      CLK : in STD_LOGIC;
      CLR : in STD_LOGIC;
      DATA : in STD_LOGIC_VECTOR(7 downto 0);
      Q : out STD_LOGIC_VECTOR(7 downto 0));
end component;

signal CE_U1 : STD_LOGIC;
signal CE_U2 : STD_LOGIC;
signal cur_FR : STD_LOGIC_VECTOR (5 downto 0);
signal cur_PR : STD_LOGIC_VECTOR (5 downto 0);
signal def_FR : STD_LOGIC_VECTOR (5 downto 0);
signal VAL : STD_LOGIC_VECTOR (7 downto 0);
signal VAL1 : STD_LOGIC_VECTOR (7 downto 0);
signal VAL2 : STD_LOGIC_VECTOR (7 downto 0);
signal VAL3 : STD_LOGIC_VECTOR (7 downto 0);
signal VAL4 : STD_LOGIC_VECTOR (7 downto 0);
signal PRFR : STD_LOGIC_VECTOR (5 downto 0);

begin

U1 : generator_reg6
  port map(
       CE => CE_U1,
       CLK => CLK,
       CLR => CLR,
       DATA => DATA,
       Q => cur_PR);

U6 : generator_sin
  port map(
       OE => '1',
       ADDRESS => PRFR,
       Q => VAL4);

VAL <= VAL4;
U2 : generator_reg6
  port map(
       CE => CE_U2,
       CLK => CLK,
       CLR => CLR,
       DATA => DATA,
       Q => def_FR);

U3 : generator_adder
  port map(
       A => cur_PR,
       B => cur_FR,
       Q => PRFR);

U4 : generator_acc6
  port map(
       A => def_FR,
       CE => CE,
       CLR => CLR,
       CLK => CLK,
       Q => cur_FR);

U7 : generator_reg8
  port map(
       CE => CE,
       CLR => CLR,
       CLK => CLK,
       DATA => VAL,
       Q => Q);

U8 : generator_and2
  port map(
       I0 => CE,
       I1 => FR,
       O => CE_U2);

U9 : generator_and2
  port map(
       I0 => CE,
       I1 => PR,
       O => CE_U1);

end architecture generator_arch;