generator.fit.smsg

FPGA开发光盘各章节实例的设计工程与源码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 10 11:56:35 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off generator -c generator
Info: Selected device EP1S10F780C5 for design "generator"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 80 of 80 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S10F780C5ES is compatible
    Info: Device EP1S20F780C5 is compatible
    Info: Device EP1S25F780C5 is compatible
    Info: Device EP1S30F780C5 is compatible
    Info: Device EP1S30F780C5_HARDCOPY_FPGA_PROTOTYPE is compatible
    Info: Device EP1S40F780C5 is compatible
    Info: Device EP1S40F780C5_HARDCOPY_FPGA_PROTOTYPE is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location H12
Warning: No exact pin location assignment(s) for 19 pins of 19 total pins
    Info: Pin Q[0] not assigned to an exact location on the device
    Info: Pin Q[1] not assigned to an exact location on the device
    Info: Pin Q[2] not assigned to an exact location on the device
    Info: Pin Q[3] not assigned to an exact location on the device
    Info: Pin Q[4] not assigned to an exact location on the device
    Info: Pin Q[5] not assigned to an exact location on the device
    Info: Pin Q[6] not assigned to an exact location on the device
    Info: Pin Q[7] not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
    Info: Pin CLR not assigned to an exact location on the device
    Info: Pin CE not assigned to an exact location on the device
    Info: Pin DATA[4] not assigned to an exact location on the device
    Info: Pin PR not assigned to an exact location on the device
    Info: Pin DATA[1] not assigned to an exact location on the device
    Info: Pin DATA[5] not assigned to an exact location on the device
    Info: Pin DATA[2] not assigned to an exact location on the device
    Info: Pin DATA[0] not assigned to an exact location on the device
    Info: Pin DATA[3] not assigned to an exact location on the device
    Info: Pin FR not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN R25
Info: Automatically promoted some destinations of signal "CLR" to use Global clock in PIN R27
    Info: Destination "generator_acc6:U4|Q[0]" may be non-global or may not use global clock
    Info: Destination "generator_acc6:U4|Q[1]" may be non-global or may not use global clock
    Info: Destination "generator_acc6:U4|Q[2]" may be non-global or may not use global clock
    Info: Destination "generator_acc6:U4|Q[3]" may be non-global or may not use global clock
    Info: Destination "generator_acc6:U4|Q[4]" may be non-global or may not use global clock
    Info: Destination "generator_acc6:U4|Q[5]" may be non-global or may not use global clock
    Info: Destination "generator_acc6:U4|Q[5]~281" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 17 (unused VREF, 3.30 VCCIO, 9 input, 8 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  46 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  54 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  55 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.108 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y17; Fanout = 3; REG Node = 'generator_acc6:U4|Q[0]'
    Info: 2: + IC(0.511 ns) + CELL(0.443 ns) = 0.954 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3|Q[0]~40'
    Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 1.012 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3|Q[1]~34'
    Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 1.070 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3|Q[2]~38'
    Info: 5: + IC(0.000 ns) + CELL(0.214 ns) = 1.284 ns; Loc. = LAB_X8_Y17; Fanout = 2; COMB Node = 'generator_adder:U3|Q[3]~42'
    Info: 6: + IC(0.000 ns) + CELL(0.469 ns) = 1.753 ns; Loc. = LAB_X8_Y17; Fanout = 24; COMB Node = 'generator_adder:U3|Q[5]~35'
    Info: 7: + IC(0.903 ns) + CELL(0.183 ns) = 2.839 ns; Loc. = LAB_X8_Y18; Fanout = 1; COMB Node = 'generator_sin:U6|Mux1~163'
    Info: 8: + IC(0.393 ns) + CELL(0.075 ns) = 3.307 ns; Loc. = LAB_X8_Y18; Fanout = 1; COMB Node = 'generator_sin:U6|Mux1~164'
    Info: 9: + IC(0.343 ns) + CELL(0.458 ns) = 4.108 ns; Loc. = LAB_X7_Y18; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[6]'
    Info: Total cell delay = 1.958 ns ( 47.66 % )
    Info: Total interconnect delay = 2.150 ns ( 52.34 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y10 to location X9_Y20
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 203 megabytes of memory during processing
    Info: Processing ended: Mon Dec 10 11:56:50 2007
    Info: Elapsed time: 00:00:15