generator.vwf

来自「FPGA开发光盘各章节实例的设计工程与源码」· VWF 代码 · 共 1,694 行 · 第 1/2 页

VWF
1,694 行
字号
12
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}

TRANSITION_LIST("Q[2]")
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	NODE
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}

TRANSITION_LIST("Q[1]")
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	}
}

TRANSITION_LIST("Q[0]")
{
	NODE
	{
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	}
}

DISPLAY_LINE
{
	CHANNEL = "CLK";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "CLR";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "CE";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "DATA";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
	CHILDREN = 4, 5, 6, 7, 8, 9;
}

DISPLAY_LINE
{
	CHANNEL = "DATA[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "DATA[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "DATA[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "DATA[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "DATA[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "DATA[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "PR";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "FR";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "Q";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 12;
	TREE_LEVEL = 0;
	CHILDREN = 13, 14, 15, 16, 17, 18, 19, 20;
}

DISPLAY_LINE
{
	CHANNEL = "Q[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 12;
}

DISPLAY_LINE
{
	CHANNEL = "Q[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 12;
}

TIME_BAR
{
	TIME = 3445000;
	MASTER = TRUE;
}
;
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generator.vwf - 源码说明

本页面展示了「FPGA开发光盘各章节实例的设计工程与源码」中的 generator.vwf 源码文件，采用 VWF 编程语言编写，共 1,694 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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