generator.tan.summary

FPGA开发光盘各章节实例的设计工程与源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.439 ns
From           : CE
To             : generator_reg6:U2|TEMP_Q_0[2]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.349 ns
From           : generator_reg8:U7|TEMP_Q_1[1]
To             : Q[1]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.436 ns
From           : CLR
To             : generator_acc6:U4|Q[2]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 230.31 MHz ( period = 4.342 ns )
From           : generator_acc6:U4|Q[0]
To             : generator_reg8:U7|TEMP_Q_1[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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