generator_acc6.vhd

来自「FPGA开发光盘各章节实例的设计工程与源码」· VHDL 代码 · 共 33 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity generator_acc6 is
    port(
	      A   : in STD_LOGIC_VECTOR(5 downto 0);
	      CE  : in STD_LOGIC;
	      CLK : in STD_LOGIC;
	      CLR : in STD_LOGIC;
	      Q   : out STD_LOGIC_VECTOR(5 downto 0)
	    );
end entity;

architecture rtl of generator_acc6 is

begin

	process (CLK,CE,A,CLR)
	begin
		if (clk'event and clk='1') then
			if clr='1' then
				Q <= (others=>'0');
			else
				if ce='1' then
					Q <= A + 1;
				end if;
			end if;
		end if;
	end process;

end architecture rtl;