generator_adder.vhd

来自「FPGA开发光盘各章节实例的设计工程与源码」· VHDL 代码 · 共 30 行

--加法器模块generator_adder.vhd文件：
------------------------------------------------------------------------------------
-- DESCRIPTION   :  cascadable Adder
--                  Width: 6
--
-- 
------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity generator_adder is
	port (
		A, B : in std_logic_vector (5 downto 0);
		Q : out std_logic_vector (5 downto 0)
	);
end entity;

-- End of automatically maintained section

architecture add_anGen_arch of generator_adder is
begin

	process (A, B)
	begin
		Q <= A + B;
	end process;

end architecture add_anGen_arch;