generator.vqm

FPGA开发光盘各章节实例的设计工程与源码

input q_39_95 ;
input q_39_72_0 ;
input q_39_98 ;
input q_39_84_a0 ;
input CE_c ;
input CLR_c ;
input q_add5 ;
input q_add4 ;
input q_add2 ;
input q_39_107_a ;
input CLK_c ;
wire Q_0 ;
wire Q_1 ;
wire Q_2 ;
wire Q_3 ;
wire Q_4 ;
wire Q_5 ;
wire Q_6 ;
wire Q_7 ;
wire q_39_101 ;
wire q_39_17_0 ;
wire q_39_28_0_a1 ;
wire q_39_23_0 ;
wire q_39_34_0 ;
wire q_39_40_0 ;
wire q_39_48_0 ;
wire q_39_52_0 ;
wire q_39_66_0_c ;
wire q_39_62_0 ;
wire q_39_64_0 ;
wire q_39_95 ;
wire q_39_72_0 ;
wire q_39_98 ;
wire q_39_84_a0 ;
wire CE_c ;
wire CLR_c ;
wire q_add5 ;
wire q_add4 ;
wire q_add2 ;
wire q_39_107_a ;
wire CLK_c ;
wire GND ;
wire VCC ;
// @11:34
  stratix_lcell Q_7_ (
	.regout(Q_7),
	.clk(CLK_c),
	.dataa(q_39_107_a),
	.datab(q_add2),
	.datac(q_add4),
	.datad(q_add5),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_7_.operation_mode="normal";
defparam Q_7_.output_mode="reg_only";
defparam Q_7_.lut_mask="0bd0";
defparam Q_7_.synch_mode="off";
defparam Q_7_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_6_ (
	.regout(Q_6),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_84_a0),
	.datac(q_39_98),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_6_.operation_mode="normal";
defparam Q_6_.output_mode="reg_only";
defparam Q_6_.lut_mask="3131";
defparam Q_6_.synch_mode="off";
defparam Q_6_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_5_ (
	.regout(Q_5),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_72_0),
	.datac(q_39_95),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_5_.operation_mode="normal";
defparam Q_5_.output_mode="reg_only";
defparam Q_5_.lut_mask="b1b1";
defparam Q_5_.synch_mode="off";
defparam Q_5_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_4_ (
	.regout(Q_4),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_64_0),
	.datac(q_39_62_0),
	.datad(q_39_66_0_c),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_4_.operation_mode="normal";
defparam Q_4_.output_mode="reg_only";
defparam Q_4_.lut_mask="dda0";
defparam Q_4_.synch_mode="off";
defparam Q_4_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_3_ (
	.regout(Q_3),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_52_0),
	.datac(q_39_48_0),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_3_.operation_mode="normal";
defparam Q_3_.output_mode="reg_only";
defparam Q_3_.lut_mask="2727";
defparam Q_3_.synch_mode="off";
defparam Q_3_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_2_ (
	.regout(Q_2),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_40_0),
	.datac(q_39_34_0),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_2_.operation_mode="normal";
defparam Q_2_.output_mode="reg_only";
defparam Q_2_.lut_mask="2727";
defparam Q_2_.synch_mode="off";
defparam Q_2_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_1_ (
	.regout(Q_1),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_23_0),
	.datac(q_39_28_0_a1),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_1_.operation_mode="normal";
defparam Q_1_.output_mode="reg_only";
defparam Q_1_.lut_mask="0b0b";
defparam Q_1_.synch_mode="off";
defparam Q_1_.sum_lutc_input="datac";
// @11:34
  stratix_lcell Q_0_ (
	.regout(Q_0),
	.clk(CLK_c),
	.dataa(q_add5),
	.datab(q_39_17_0),
	.datac(q_39_101),
	.aclr(CLR_c),
	.ena(CE_c)
);
defparam Q_0_.operation_mode="normal";
defparam Q_0_.output_mode="reg_only";
defparam Q_0_.lut_mask="7272";
defparam Q_0_.synch_mode="off";
defparam Q_0_.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_reg8 */

module generator_and2 (
  CE_c,
  FR_c,
  O_0_and2
);
input CE_c ;
input FR_c ;
output O_0_and2 ;
wire CE_c ;
wire FR_c ;
wire O_0_and2 ;
wire GND ;
wire VCC ;
// @8:23
  stratix_lcell O_0_and2_0 (
	.combout(O_0_and2),
	.dataa(FR_c),
	.datab(CE_c)
);
defparam O_0_and2_0.operation_mode="normal";
defparam O_0_and2_0.output_mode="comb_only";
defparam O_0_and2_0.lut_mask="8888";
defparam O_0_and2_0.synch_mode="off";
defparam O_0_and2_0.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_and2 */

module generator_and2_1 (
  CE_c,
  PR_c,
  O_0_and2
);
input CE_c ;
input PR_c ;
output O_0_and2 ;
wire CE_c ;
wire PR_c ;
wire O_0_and2 ;
wire GND ;
wire VCC ;
// @8:23
  stratix_lcell O_0_and2_0 (
	.combout(O_0_and2),
	.dataa(PR_c),
	.datab(CE_c)
);
defparam O_0_and2_0.operation_mode="normal";
defparam O_0_and2_0.output_mode="comb_only";
defparam O_0_and2_0.lut_mask="8888";
defparam O_0_and2_0.synch_mode="off";
defparam O_0_and2_0.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_and2_1 */

module generator (
  DATA,
  PR,
  FR,
  CLR,
  CE,
  Q,
  CLK
);
input [5:0] DATA ;
input PR ;
input FR ;
input CLR ;
input CE ;
output [7:0] Q /* synthesis syn_tristate = 1 */;
input CLK ;
wire PR ;
wire FR ;
wire CLR ;
wire CE ;
wire CLK ;
wire [7:0] U7_Q;
wire [5:0] DATA_c;
wire [5:0] U1_Q;
wire [5:0] U4_un1_a_0_and2;
wire [5:0] U4_Q;
wire VCC ;
wire GND ;
wire CLK_c ;
wire CE_c ;
wire CLR_c ;
wire FR_c ;
wire PR_c ;
wire U9_O_0_and2 ;
wire U6_q_39_98 ;
wire U6_q_39_95 ;
wire U6_q_39_64_0 ;
wire U6_q_39_62_0 ;
wire U6_q_39_23_0 ;
wire U6_q_39_72_0 ;
wire U6_q_39_40_0 ;
wire U6_q_39_107_a ;
wire U6_q_39_101 ;
wire U6_q_39_84_a0 ;
wire U6_q_39_52_0 ;
wire U6_q_39_48_0 ;
wire U6_q_39_34_0 ;
wire U6_q_39_28_0_a1 ;
wire U3_q_add3 ;
wire U3_q_add2 ;
wire U3_q_add1 ;
wire U3_q_add0 ;
wire U6_q_39_17_0 ;
wire U3_q_add4 ;
wire U3_q_add5 ;
wire U6_q_39_66_0_c ;
wire U8_O_0_and2 ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @12:38
  stratix_io CLK_in (
	.padio(CLK),
	.combout(CLK_c)
);
defparam CLK_in.operation_mode = "input";
// @12:37
  stratix_io Q_out_7_ (
	.padio(Q[7]),
	.datain(U7_Q[7]),
	.oe(VCC)
);
defparam Q_out_7_.operation_mode = "output";
// @12:37
  stratix_io Q_out_6_ (
	.padio(Q[6]),
	.datain(U7_Q[6]),
	.oe(VCC)
);
defparam Q_out_6_.operation_mode = "output";
// @12:37
  stratix_io Q_out_5_ (
	.padio(Q[5]),
	.datain(U7_Q[5]),
	.oe(VCC)
);
defparam Q_out_5_.operation_mode = "output";
// @12:37
  stratix_io Q_out_4_ (
	.padio(Q[4]),
	.datain(U7_Q[4]),
	.oe(VCC)
);
defparam Q_out_4_.operation_mode = "output";
// @12:37
  stratix_io Q_out_3_ (
	.padio(Q[3]),
	.datain(U7_Q[3]),
	.oe(VCC)
);
defparam Q_out_3_.operation_mode = "output";
// @12:37
  stratix_io Q_out_2_ (
	.padio(Q[2]),
	.datain(U7_Q[2]),
	.oe(VCC)
);
defparam Q_out_2_.operation_mode = "output";
// @12:37
  stratix_io Q_out_1_ (
	.padio(Q[1]),
	.datain(U7_Q[1]),
	.oe(VCC)
);
defparam Q_out_1_.operation_mode = "output";
// @12:37
  stratix_io Q_out_0_ (
	.padio(Q[0]),
	.datain(U7_Q[0]),
	.oe(VCC)
);
defparam Q_out_0_.operation_mode = "output";
// @12:36
  stratix_io CE_in (
	.padio(CE),
	.combout(CE_c)
);
defparam CE_in.operation_mode = "input";
// @12:35
  stratix_io CLR_in (
	.padio(CLR),
	.combout(CLR_c)
);
defparam CLR_in.operation_mode = "input";
// @12:34
  stratix_io FR_in (
	.padio(FR),
	.combout(FR_c)
);
defparam FR_in.operation_mode = "input";
// @12:33
  stratix_io PR_in (
	.padio(PR),
	.combout(PR_c)
);
defparam PR_in.operation_mode = "input";
// @12:32
  stratix_io DATA_in_5_ (
	.padio(DATA[5]),
	.combout(DATA_c[5])
);
defparam DATA_in_5_.operation_mode = "input";
// @12:32
  stratix_io DATA_in_4_ (
	.padio(DATA[4]),
	.combout(DATA_c[4])
);
defparam DATA_in_4_.operation_mode = "input";
// @12:32
  stratix_io DATA_in_3_ (
	.padio(DATA[3]),
	.combout(DATA_c[3])
);
defparam DATA_in_3_.operation_mode = "input";
// @12:32
  stratix_io DATA_in_2_ (
	.padio(DATA[2]),
	.combout(DATA_c[2])
);
defparam DATA_in_2_.operation_mode = "input";
// @12:32
  stratix_io DATA_in_1_ (
	.padio(DATA[1]),
	.combout(DATA_c[1])
);
defparam DATA_in_1_.operation_mode = "input";
// @12:32
  stratix_io DATA_in_0_ (
	.padio(DATA[0]),
	.combout(DATA_c[0])
);
defparam DATA_in_0_.operation_mode = "input";
// @12:109
  generator_reg6 U1 (
	.DATA_c_0(DATA_c[0]),
	.DATA_c_1(DATA_c[1]),
	.DATA_c_2(DATA_c[2]),
	.DATA_c_3(DATA_c[3]),
	.DATA_c_4(DATA_c[4]),
	.DATA_c_5(DATA_c[5]),
	.Q_0(U1_Q[0]),
	.Q_1(U1_Q[1]),
	.Q_2(U1_Q[2]),
	.Q_3(U1_Q[3]),
	.Q_4(U1_Q[4]),
	.Q_5(U1_Q[5]),
	.O_0_and2(U9_O_0_and2),
	.CLR_c(CLR_c),
	.CLK_c(CLK_c)
);
// @12:117
  generator_sin U6 (
	.q_39_98(U6_q_39_98),
	.q_39_95(U6_q_39_95),
	.q_39_64_0(U6_q_39_64_0),
	.q_39_62_0(U6_q_39_62_0),
	.q_39_23_0(U6_q_39_23_0),
	.q_39_72_0(U6_q_39_72_0),
	.q_39_40_0(U6_q_39_40_0),
	.q_39_107_a(U6_q_39_107_a),
	.q_39_101(U6_q_39_101),
	.q_39_84_a0(U6_q_39_84_a0),
	.q_39_52_0(U6_q_39_52_0),
	.q_39_48_0(U6_q_39_48_0),
	.q_39_34_0(U6_q_39_34_0),
	.q_39_28_0_a1(U6_q_39_28_0_a1),
	.q_add3(U3_q_add3),
	.q_add2(U3_q_add2),
	.q_add1(U3_q_add1),
	.q_add0(U3_q_add0),
	.q_39_17_0(U6_q_39_17_0),
	.q_add4(U3_q_add4),
	.q_add5(U3_q_add5),
	.q_39_66_0_c(U6_q_39_66_0_c)
);
// @12:125
  generator_reg6_1 U2 (
	.DATA_c_5(DATA_c[5]),
	.DATA_c_4(DATA_c[4]),
	.DATA_c_3(DATA_c[3]),
	.DATA_c_2(DATA_c[2]),
	.DATA_c_1(DATA_c[1]),
	.DATA_c_0(DATA_c[0]),
	.un1_a_0_and2_0(U4_un1_a_0_and2[0]),
	.un1_a_0_and2_1(U4_un1_a_0_and2[1]),
	.un1_a_0_and2_2(U4_un1_a_0_and2[2]),
	.un1_a_0_and2_3(U4_un1_a_0_and2[3]),
	.un1_a_0_and2_4(U4_un1_a_0_and2[4]),
	.un1_a_0_and2_5(U4_un1_a_0_and2[5]),
	.O_0_and2(U8_O_0_and2),
	.CLR_c(CLR_c),
	.CE_c(CE_c),
	.CLK_c(CLK_c)
);
// @12:133
  generator_adder U3 (
	.Q_0_0(U4_Q[0]),
	.Q_0_1(U4_Q[1]),
	.Q_0_2(U4_Q[2]),
	.Q_0_3(U4_Q[3]),
	.Q_0_4(U4_Q[4]),
	.Q_0_5(U4_Q[5]),
	.Q_0(U1_Q[0]),
	.Q_1(U1_Q[1]),
	.Q_2(U1_Q[2]),
	.Q_3(U1_Q[3]),
	.Q_4(U1_Q[4]),
	.Q_5(U1_Q[5]),
	.q_add0(U3_q_add0),
	.q_add1(U3_q_add1),
	.q_add2(U3_q_add2),
	.q_add3(U3_q_add3),
	.q_add4(U3_q_add4),
	.q_add5(U3_q_add5)
);
// @12:139
  generator_acc6 U4 (
	.un1_a_0_and2_5(U4_un1_a_0_and2[5]),
	.un1_a_0_and2_4(U4_un1_a_0_and2[4]),
	.un1_a_0_and2_3(U4_un1_a_0_and2[3]),
	.un1_a_0_and2_2(U4_un1_a_0_and2[2]),
	.un1_a_0_and2_1(U4_un1_a_0_and2[1]),
	.un1_a_0_and2_0(U4_un1_a_0_and2[0]),
	.Q_0(U4_Q[0]),
	.Q_1(U4_Q[1]),
	.Q_2(U4_Q[2]),
	.Q_3(U4_Q[3]),
	.Q_4(U4_Q[4]),
	.Q_5(U4_Q[5]),
	.CLR_c(CLR_c),
	.CLK_c(CLK_c)
);
// @12:147
  generator_reg8 U7 (
	.Q_0(U7_Q[0]),
	.Q_1(U7_Q[1]),
	.Q_2(U7_Q[2]),
	.Q_3(U7_Q[3]),
	.Q_4(U7_Q[4]),
	.Q_5(U7_Q[5]),
	.Q_6(U7_Q[6]),
	.Q_7(U7_Q[7]),
	.q_39_101(U6_q_39_101),
	.q_39_17_0(U6_q_39_17_0),
	.q_39_28_0_a1(U6_q_39_28_0_a1),
	.q_39_23_0(U6_q_39_23_0),
	.q_39_34_0(U6_q_39_34_0),
	.q_39_40_0(U6_q_39_40_0),
	.q_39_48_0(U6_q_39_48_0),
	.q_39_52_0(U6_q_39_52_0),
	.q_39_66_0_c(U6_q_39_66_0_c),
	.q_39_62_0(U6_q_39_62_0),
	.q_39_64_0(U6_q_39_64_0),
	.q_39_95(U6_q_39_95),
	.q_39_72_0(U6_q_39_72_0),
	.q_39_98(U6_q_39_98),
	.q_39_84_a0(U6_q_39_84_a0),
	.CE_c(CE_c),
	.CLR_c(CLR_c),
	.q_add5(U3_q_add5),
	.q_add4(U3_q_add4),
	.q_add2(U3_q_add2),
	.q_39_107_a(U6_q_39_107_a),
	.CLK_c(CLK_c)
);
// @12:155
  generator_and2 U8 (
	.CE_c(CE_c),
	.FR_c(FR_c),
	.O_0_and2(U8_O_0_and2)
);
// @12:161
  generator_and2_1 U9 (
	.CE_c(CE_c),
	.PR_c(PR_c),
	.O_0_and2(U9_O_0_and2)
);
endmodule /* generator */