generator.vqm

FPGA开发光盘各章节实例的设计工程与源码

defparam q_39_62_0_0.synch_mode="off";
defparam q_39_62_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_64_0_0 (
	.combout(q_39_64_0),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_64_0_0.operation_mode="normal";
defparam q_39_64_0_0.output_mode="comb_only";
defparam q_39_64_0_0.lut_mask="03cd";
defparam q_39_64_0_0.synch_mode="off";
defparam q_39_64_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_95_0 (
	.combout(q_39_95),
	.dataa(q_add1),
	.datab(q_add2),
	.datac(q_add3),
	.datad(q_add4)
);
defparam q_39_95_0.operation_mode="normal";
defparam q_39_95_0.output_mode="comb_only";
defparam q_39_95_0.lut_mask="06af";
defparam q_39_95_0.synch_mode="off";
defparam q_39_95_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_98_0 (
	.combout(q_39_98),
	.dataa(q_add1),
	.datab(q_add2),
	.datac(q_add3),
	.datad(q_add4)
);
defparam q_39_98_0.operation_mode="normal";
defparam q_39_98_0.output_mode="comb_only";
defparam q_39_98_0.lut_mask="019f";
defparam q_39_98_0.synch_mode="off";
defparam q_39_98_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_32_0_Z (
	.combout(q_39_32_0),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2)
);
defparam q_39_32_0_Z.operation_mode="normal";
defparam q_39_32_0_Z.output_mode="comb_only";
defparam q_39_32_0_Z.lut_mask="2424";
defparam q_39_32_0_Z.synch_mode="off";
defparam q_39_32_0_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_44_0_Z (
	.combout(q_39_44_0),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2)
);
defparam q_39_44_0_Z.operation_mode="normal";
defparam q_39_44_0_Z.output_mode="comb_only";
defparam q_39_44_0_Z.lut_mask="2929";
defparam q_39_44_0_Z.synch_mode="off";
defparam q_39_44_0_Z.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_sin */

module generator_reg6_1 (
  DATA_c_5,
  DATA_c_4,
  DATA_c_3,
  DATA_c_2,
  DATA_c_1,
  DATA_c_0,
  un1_a_0_and2_0,
  un1_a_0_and2_1,
  un1_a_0_and2_2,
  un1_a_0_and2_3,
  un1_a_0_and2_4,
  un1_a_0_and2_5,
  O_0_and2,
  CLR_c,
  CE_c,
  CLK_c
);
input DATA_c_5 ;
input DATA_c_4 ;
input DATA_c_3 ;
input DATA_c_2 ;
input DATA_c_1 ;
input DATA_c_0 ;
output un1_a_0_and2_0 ;
output un1_a_0_and2_1 ;
output un1_a_0_and2_2 ;
output un1_a_0_and2_3 ;
output un1_a_0_and2_4 ;
output un1_a_0_and2_5 ;
input O_0_and2 ;
input CLR_c ;
input CE_c ;
input CLK_c ;
wire DATA_c_5 ;
wire DATA_c_4 ;
wire DATA_c_3 ;
wire DATA_c_2 ;
wire DATA_c_1 ;
wire DATA_c_0 ;
wire un1_a_0_and2_0 ;
wire un1_a_0_and2_1 ;
wire un1_a_0_and2_2 ;
wire un1_a_0_and2_3 ;
wire un1_a_0_and2_4 ;
wire un1_a_0_and2_5 ;
wire O_0_and2 ;
wire CLR_c ;
wire CE_c ;
wire CLK_c ;
wire VCC ;
wire GND ;
  stratix_lcell Q_0_ (
	.combout(un1_a_0_and2_5),
	.clk(CLK_c),
	.dataa(CE_c),
	.datac(DATA_c_0),
	.aclr(CLR_c),
	.sload(VCC),
	.ena(O_0_and2)
);
defparam Q_0_.operation_mode="normal";
defparam Q_0_.output_mode="comb_only";
defparam Q_0_.lut_mask="a0a0";
defparam Q_0_.synch_mode="on";
defparam Q_0_.sum_lutc_input="qfbk";
  stratix_lcell Q_1_ (
	.combout(un1_a_0_and2_4),
	.clk(CLK_c),
	.dataa(CE_c),
	.datac(DATA_c_1),
	.aclr(CLR_c),
	.sload(VCC),
	.ena(O_0_and2)
);
defparam Q_1_.operation_mode="normal";
defparam Q_1_.output_mode="comb_only";
defparam Q_1_.lut_mask="a0a0";
defparam Q_1_.synch_mode="on";
defparam Q_1_.sum_lutc_input="qfbk";
  stratix_lcell Q_2_ (
	.combout(un1_a_0_and2_3),
	.clk(CLK_c),
	.dataa(CE_c),
	.datac(DATA_c_2),
	.aclr(CLR_c),
	.sload(VCC),
	.ena(O_0_and2)
);
defparam Q_2_.operation_mode="normal";
defparam Q_2_.output_mode="comb_only";
defparam Q_2_.lut_mask="a0a0";
defparam Q_2_.synch_mode="on";
defparam Q_2_.sum_lutc_input="qfbk";
  stratix_lcell Q_3_ (
	.combout(un1_a_0_and2_2),
	.clk(CLK_c),
	.dataa(CE_c),
	.datac(DATA_c_3),
	.aclr(CLR_c),
	.sload(VCC),
	.ena(O_0_and2)
);
defparam Q_3_.operation_mode="normal";
defparam Q_3_.output_mode="comb_only";
defparam Q_3_.lut_mask="a0a0";
defparam Q_3_.synch_mode="on";
defparam Q_3_.sum_lutc_input="qfbk";
  stratix_lcell Q_4_ (
	.combout(un1_a_0_and2_1),
	.clk(CLK_c),
	.dataa(CE_c),
	.datac(DATA_c_4),
	.aclr(CLR_c),
	.sload(VCC),
	.ena(O_0_and2)
);
defparam Q_4_.operation_mode="normal";
defparam Q_4_.output_mode="comb_only";
defparam Q_4_.lut_mask="a0a0";
defparam Q_4_.synch_mode="on";
defparam Q_4_.sum_lutc_input="qfbk";
  stratix_lcell Q_5_ (
	.combout(un1_a_0_and2_0),
	.clk(CLK_c),
	.dataa(CE_c),
	.datac(DATA_c_5),
	.aclr(CLR_c),
	.sload(VCC),
	.ena(O_0_and2)
);
defparam Q_5_.operation_mode="normal";
defparam Q_5_.output_mode="comb_only";
defparam Q_5_.lut_mask="a0a0";
defparam Q_5_.synch_mode="on";
defparam Q_5_.sum_lutc_input="qfbk";
//@1:1
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* generator_reg6_1 */

module generator_adder (
  Q_0_0,
  Q_0_1,
  Q_0_2,
  Q_0_3,
  Q_0_4,
  Q_0_5,
  Q_0,
  Q_1,
  Q_2,
  Q_3,
  Q_4,
  Q_5,
  q_add0,
  q_add1,
  q_add2,
  q_add3,
  q_add4,
  q_add5
);
input Q_0_0 ;
input Q_0_1 ;
input Q_0_2 ;
input Q_0_3 ;
input Q_0_4 ;
input Q_0_5 ;
input Q_0 ;
input Q_1 ;
input Q_2 ;
input Q_3 ;
input Q_4 ;
input Q_5 ;
output q_add0 ;
output q_add1 ;
output q_add2 ;
output q_add3 ;
output q_add4 ;
output q_add5 ;
wire Q_0_0 ;
wire Q_0_1 ;
wire Q_0_2 ;
wire Q_0_3 ;
wire Q_0_4 ;
wire Q_0_5 ;
wire Q_0 ;
wire Q_1 ;
wire Q_2 ;
wire Q_3 ;
wire Q_4 ;
wire Q_5 ;
wire q_add0 ;
wire q_add1 ;
wire q_add2 ;
wire q_add3 ;
wire q_add4 ;
wire q_add5 ;
wire q_carry_4 ;
wire q_carry_3 ;
wire q_carry_2 ;
wire q_carry_1 ;
wire q_carry_0 ;
wire GND ;
wire VCC ;
// @7:27
  stratix_lcell q_add5_0 (
	.combout(q_add5),
	.dataa(Q_5),
	.datab(Q_0_5),
	.cin(q_carry_4)
);
defparam q_add5_0.cin_used="true";
defparam q_add5_0.operation_mode="normal";
defparam q_add5_0.output_mode="comb_only";
defparam q_add5_0.lut_mask="9696";
defparam q_add5_0.synch_mode="off";
defparam q_add5_0.sum_lutc_input="cin";
// @7:27
  stratix_lcell q_add4_0 (
	.combout(q_add4),
	.cout(q_carry_4),
	.dataa(Q_4),
	.datab(Q_0_4),
	.cin(q_carry_3)
);
defparam q_add4_0.cin_used="true";
defparam q_add4_0.operation_mode="arithmetic";
defparam q_add4_0.output_mode="comb_only";
defparam q_add4_0.lut_mask="96e8";
defparam q_add4_0.synch_mode="off";
defparam q_add4_0.sum_lutc_input="cin";
// @7:27
  stratix_lcell q_add3_0 (
	.combout(q_add3),
	.cout(q_carry_3),
	.dataa(Q_3),
	.datab(Q_0_3),
	.cin(q_carry_2)
);
defparam q_add3_0.cin_used="true";
defparam q_add3_0.operation_mode="arithmetic";
defparam q_add3_0.output_mode="comb_only";
defparam q_add3_0.lut_mask="96e8";
defparam q_add3_0.synch_mode="off";
defparam q_add3_0.sum_lutc_input="cin";
// @7:27
  stratix_lcell q_add2_0 (
	.combout(q_add2),
	.cout(q_carry_2),
	.dataa(Q_2),
	.datab(Q_0_2),
	.cin(q_carry_1)
);
defparam q_add2_0.cin_used="true";
defparam q_add2_0.operation_mode="arithmetic";
defparam q_add2_0.output_mode="comb_only";
defparam q_add2_0.lut_mask="96e8";
defparam q_add2_0.synch_mode="off";
defparam q_add2_0.sum_lutc_input="cin";
// @7:27
  stratix_lcell q_add1_0 (
	.combout(q_add1),
	.cout(q_carry_1),
	.dataa(Q_1),
	.datab(Q_0_1),
	.cin(q_carry_0)
);
defparam q_add1_0.cin_used="true";
defparam q_add1_0.operation_mode="arithmetic";
defparam q_add1_0.output_mode="comb_only";
defparam q_add1_0.lut_mask="96e8";
defparam q_add1_0.synch_mode="off";
defparam q_add1_0.sum_lutc_input="cin";
// @7:27
  stratix_lcell q_add0_0 (
	.combout(q_add0),
	.cout(q_carry_0),
	.dataa(Q_0),
	.datab(Q_0_0)
);
defparam q_add0_0.operation_mode="arithmetic";
defparam q_add0_0.output_mode="comb_only";
defparam q_add0_0.lut_mask="6688";
defparam q_add0_0.synch_mode="off";
defparam q_add0_0.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_adder */

module generator_acc6 (
  un1_a_0_and2_5,
  un1_a_0_and2_4,
  un1_a_0_and2_3,
  un1_a_0_and2_2,
  un1_a_0_and2_1,
  un1_a_0_and2_0,
  Q_0,
  Q_1,
  Q_2,
  Q_3,
  Q_4,
  Q_5,
  CLR_c,
  CLK_c
);
input un1_a_0_and2_5 ;
input un1_a_0_and2_4 ;
input un1_a_0_and2_3 ;
input un1_a_0_and2_2 ;
input un1_a_0_and2_1 ;
input un1_a_0_and2_0 ;
output Q_0 ;
output Q_1 ;
output Q_2 ;
output Q_3 ;
output Q_4 ;
output Q_5 ;
input CLR_c ;
input CLK_c ;
wire un1_a_0_and2_5 ;
wire un1_a_0_and2_4 ;
wire un1_a_0_and2_3 ;
wire un1_a_0_and2_2 ;
wire un1_a_0_and2_1 ;
wire un1_a_0_and2_0 ;
wire Q_0 ;
wire Q_1 ;
wire Q_2 ;
wire Q_3 ;
wire Q_4 ;
wire Q_5 ;
wire CLR_c ;
wire CLK_c ;
wire reg_q_4_carry_4 ;
wire reg_q_4_carry_3 ;
wire reg_q_4_carry_2 ;
wire reg_q_4_carry_1 ;
wire reg_q_4_carry_0 ;
wire GND ;
wire VCC ;
// @6:39
  stratix_lcell Q_5_ (
	.regout(Q_5),
	.clk(CLK_c),
	.dataa(Q_5),
	.datab(un1_a_0_and2_0),
	.aclr(CLR_c),
	.cin(reg_q_4_carry_4)
);
defparam Q_5_.cin_used="true";
defparam Q_5_.operation_mode="normal";
defparam Q_5_.output_mode="reg_only";
defparam Q_5_.lut_mask="9696";
defparam Q_5_.synch_mode="off";
defparam Q_5_.sum_lutc_input="cin";
// @6:39
  stratix_lcell Q_4_ (
	.regout(Q_4),
	.cout(reg_q_4_carry_4),
	.clk(CLK_c),
	.dataa(Q_4),
	.datab(un1_a_0_and2_1),
	.aclr(CLR_c),
	.cin(reg_q_4_carry_3)
);
defparam Q_4_.cin_used="true";
defparam Q_4_.operation_mode="arithmetic";
defparam Q_4_.output_mode="reg_only";
defparam Q_4_.lut_mask="96e8";
defparam Q_4_.synch_mode="off";
defparam Q_4_.sum_lutc_input="cin";
// @6:39
  stratix_lcell Q_3_ (
	.regout(Q_3),
	.cout(reg_q_4_carry_3),
	.clk(CLK_c),
	.dataa(Q_3),
	.datab(un1_a_0_and2_2),
	.aclr(CLR_c),
	.cin(reg_q_4_carry_2)
);
defparam Q_3_.cin_used="true";
defparam Q_3_.operation_mode="arithmetic";
defparam Q_3_.output_mode="reg_only";
defparam Q_3_.lut_mask="96e8";
defparam Q_3_.synch_mode="off";
defparam Q_3_.sum_lutc_input="cin";
// @6:39
  stratix_lcell Q_2_ (
	.regout(Q_2),
	.cout(reg_q_4_carry_2),
	.clk(CLK_c),
	.dataa(Q_2),
	.datab(un1_a_0_and2_3),
	.aclr(CLR_c),
	.cin(reg_q_4_carry_1)
);
defparam Q_2_.cin_used="true";
defparam Q_2_.operation_mode="arithmetic";
defparam Q_2_.output_mode="reg_only";
defparam Q_2_.lut_mask="96e8";
defparam Q_2_.synch_mode="off";
defparam Q_2_.sum_lutc_input="cin";
// @6:39
  stratix_lcell Q_1_ (
	.regout(Q_1),
	.cout(reg_q_4_carry_1),
	.clk(CLK_c),
	.dataa(Q_1),
	.datab(un1_a_0_and2_4),
	.aclr(CLR_c),
	.cin(reg_q_4_carry_0)
);
defparam Q_1_.cin_used="true";
defparam Q_1_.operation_mode="arithmetic";
defparam Q_1_.output_mode="reg_only";
defparam Q_1_.lut_mask="96e8";
defparam Q_1_.synch_mode="off";
defparam Q_1_.sum_lutc_input="cin";
// @6:39
  stratix_lcell Q_0_ (
	.regout(Q_0),
	.cout(reg_q_4_carry_0),
	.clk(CLK_c),
	.dataa(Q_0),
	.datab(un1_a_0_and2_5),
	.aclr(CLR_c)
);
defparam Q_0_.operation_mode="arithmetic";
defparam Q_0_.output_mode="reg_only";
defparam Q_0_.lut_mask="6688";
defparam Q_0_.synch_mode="off";
defparam Q_0_.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_acc6 */

module generator_reg8 (
  Q_0,
  Q_1,
  Q_2,
  Q_3,
  Q_4,
  Q_5,
  Q_6,
  Q_7,
  q_39_101,
  q_39_17_0,
  q_39_28_0_a1,
  q_39_23_0,
  q_39_34_0,
  q_39_40_0,
  q_39_48_0,
  q_39_52_0,
  q_39_66_0_c,
  q_39_62_0,
  q_39_64_0,
  q_39_95,
  q_39_72_0,
  q_39_98,
  q_39_84_a0,
  CE_c,
  CLR_c,
  q_add5,
  q_add4,
  q_add2,
  q_39_107_a,
  CLK_c
);
output Q_0 ;
output Q_1 ;
output Q_2 ;
output Q_3 ;
output Q_4 ;
output Q_5 ;
output Q_6 ;
output Q_7 ;
input q_39_101 ;
input q_39_17_0 ;
input q_39_28_0_a1 ;
input q_39_23_0 ;
input q_39_34_0 ;
input q_39_40_0 ;
input q_39_48_0 ;
input q_39_52_0 ;
input q_39_66_0_c ;
input q_39_62_0 ;
input q_39_64_0 ;