generator.vqm

FPGA开发光盘各章节实例的设计工程与源码

//
// Written by Synplify
// Synplify 7.3, Build 173R.
// Sat Jul 16 15:28:36 2005
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\program files\synplicity\synplify_73\lib\vhd\std.vhd "
// file 2 "\d:\924lyj\924\generator_sin.vhd "
// file 3 "\c:\program files\synplicity\synplify_73\lib\vhd\std1164.vhd "
// file 4 "\c:\program files\synplicity\synplify_73\lib\vhd\arith.vhd "
// file 5 "\c:\program files\synplicity\synplify_73\lib\vhd\unsigned.vhd "
// file 6 "\d:\924lyj\924\generator_acc6.vhd "
// file 7 "\d:\924lyj\924\generator_adder.vhd "
// file 8 "\d:\924lyj\924\generator_and2.vhd "
// file 9 "\d:\924lyj\924\generator_mux.vhd "
// file 10 "\d:\924lyj\924\generator_reg6.vhd "
// file 11 "\d:\924lyj\924\generator_reg8.vhd "
// file 12 "\d:\924lyj\924\generator.vhd "

module generator_reg6 (
  DATA_c_0,
  DATA_c_1,
  DATA_c_2,
  DATA_c_3,
  DATA_c_4,
  DATA_c_5,
  Q_0,
  Q_1,
  Q_2,
  Q_3,
  Q_4,
  Q_5,
  O_0_and2,
  CLR_c,
  CLK_c
);
input DATA_c_0 ;
input DATA_c_1 ;
input DATA_c_2 ;
input DATA_c_3 ;
input DATA_c_4 ;
input DATA_c_5 ;
output Q_0 ;
output Q_1 ;
output Q_2 ;
output Q_3 ;
output Q_4 ;
output Q_5 ;
input O_0_and2 ;
input CLR_c ;
input CLK_c ;
wire DATA_c_0 ;
wire DATA_c_1 ;
wire DATA_c_2 ;
wire DATA_c_3 ;
wire DATA_c_4 ;
wire DATA_c_5 ;
wire Q_0 ;
wire Q_1 ;
wire Q_2 ;
wire Q_3 ;
wire Q_4 ;
wire Q_5 ;
wire O_0_and2 ;
wire CLR_c ;
wire CLK_c ;
wire GND ;
wire VCC ;
// @10:33
  stratix_lcell Q_5_ (
	.regout(Q_5),
	.clk(CLK_c),
	.datad(DATA_c_5),
	.aclr(CLR_c),
	.ena(O_0_and2)
);
defparam Q_5_.operation_mode="normal";
defparam Q_5_.output_mode="reg_only";
defparam Q_5_.lut_mask="ff00";
defparam Q_5_.synch_mode="off";
defparam Q_5_.sum_lutc_input="datac";
// @10:33
  stratix_lcell Q_4_ (
	.regout(Q_4),
	.clk(CLK_c),
	.datad(DATA_c_4),
	.aclr(CLR_c),
	.ena(O_0_and2)
);
defparam Q_4_.operation_mode="normal";
defparam Q_4_.output_mode="reg_only";
defparam Q_4_.lut_mask="ff00";
defparam Q_4_.synch_mode="off";
defparam Q_4_.sum_lutc_input="datac";
// @10:33
  stratix_lcell Q_3_ (
	.regout(Q_3),
	.clk(CLK_c),
	.datad(DATA_c_3),
	.aclr(CLR_c),
	.ena(O_0_and2)
);
defparam Q_3_.operation_mode="normal";
defparam Q_3_.output_mode="reg_only";
defparam Q_3_.lut_mask="ff00";
defparam Q_3_.synch_mode="off";
defparam Q_3_.sum_lutc_input="datac";
// @10:33
  stratix_lcell Q_2_ (
	.regout(Q_2),
	.clk(CLK_c),
	.datad(DATA_c_2),
	.aclr(CLR_c),
	.ena(O_0_and2)
);
defparam Q_2_.operation_mode="normal";
defparam Q_2_.output_mode="reg_only";
defparam Q_2_.lut_mask="ff00";
defparam Q_2_.synch_mode="off";
defparam Q_2_.sum_lutc_input="datac";
// @10:33
  stratix_lcell Q_1_ (
	.regout(Q_1),
	.clk(CLK_c),
	.datad(DATA_c_1),
	.aclr(CLR_c),
	.ena(O_0_and2)
);
defparam Q_1_.operation_mode="normal";
defparam Q_1_.output_mode="reg_only";
defparam Q_1_.lut_mask="ff00";
defparam Q_1_.synch_mode="off";
defparam Q_1_.sum_lutc_input="datac";
// @10:33
  stratix_lcell Q_0_ (
	.regout(Q_0),
	.clk(CLK_c),
	.datad(DATA_c_0),
	.aclr(CLR_c),
	.ena(O_0_and2)
);
defparam Q_0_.operation_mode="normal";
defparam Q_0_.output_mode="reg_only";
defparam Q_0_.lut_mask="ff00";
defparam Q_0_.synch_mode="off";
defparam Q_0_.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* generator_reg6 */

module generator_sin (
  q_39_98,
  q_39_95,
  q_39_64_0,
  q_39_62_0,
  q_39_23_0,
  q_39_72_0,
  q_39_40_0,
  q_39_107_a,
  q_39_101,
  q_39_84_a0,
  q_39_52_0,
  q_39_48_0,
  q_39_34_0,
  q_39_28_0_a1,
  q_add3,
  q_add2,
  q_add1,
  q_add0,
  q_39_17_0,
  q_add4,
  q_add5,
  q_39_66_0_c
);
output q_39_98 ;
output q_39_95 ;
output q_39_64_0 ;
output q_39_62_0 ;
output q_39_23_0 ;
output q_39_72_0 ;
output q_39_40_0 ;
output q_39_107_a ;
output q_39_101 ;
output q_39_84_a0 ;
output q_39_52_0 ;
output q_39_48_0 ;
output q_39_34_0 ;
output q_39_28_0_a1 ;
input q_add3 ;
input q_add2 ;
input q_add1 ;
input q_add0 ;
output q_39_17_0 ;
input q_add4 ;
input q_add5 ;
output q_39_66_0_c ;
wire q_39_98 ;
wire q_39_95 ;
wire q_39_64_0 ;
wire q_39_62_0 ;
wire q_39_23_0 ;
wire q_39_72_0 ;
wire q_39_40_0 ;
wire q_39_107_a ;
wire q_39_101 ;
wire q_39_84_a0 ;
wire q_39_52_0 ;
wire q_39_48_0 ;
wire q_39_34_0 ;
wire q_39_28_0_a1 ;
wire q_add3 ;
wire q_add2 ;
wire q_add1 ;
wire q_add0 ;
wire q_39_17_0 ;
wire q_add4 ;
wire q_add5 ;
wire q_39_66_0_c ;
wire q_39_59_0 ;
wire q_39_56_0 ;
wire q_39_17_0_a ;
wire q_39_28_0_a1_a ;
wire q_39_34_0_a ;
wire q_39_32_0 ;
wire q_39_48_0_a ;
wire q_39_44_0 ;
wire q_39_52_0_a ;
wire q_39_84_a0_a ;
wire q_39_101_a ;
wire q_39_40_0_a ;
wire q_39_72_0_a ;
wire q_39_23_0_a ;
wire GND ;
wire VCC ;
  stratix_lcell q_39_66_0_c_0 (
	.combout(q_39_66_0_c),
	.dataa(q_add5),
	.datab(q_add4),
	.datac(q_39_59_0),
	.datad(q_39_56_0)
);
defparam q_39_66_0_c_0.operation_mode="normal";
defparam q_39_66_0_c_0.output_mode="comb_only";
defparam q_39_66_0_c_0.lut_mask="d9c8";
defparam q_39_66_0_c_0.synch_mode="off";
defparam q_39_66_0_c_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_17_0_0 (
	.combout(q_39_17_0),
	.dataa(q_39_17_0_a),
	.datab(q_add0),
	.datac(q_add1),
	.datad(q_add4)
);
defparam q_39_17_0_0.operation_mode="normal";
defparam q_39_17_0_0.output_mode="comb_only";
defparam q_39_17_0_0.lut_mask="68d5";
defparam q_39_17_0_0.synch_mode="off";
defparam q_39_17_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_17_0_a_Z (
	.combout(q_39_17_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_17_0_a_Z.operation_mode="normal";
defparam q_39_17_0_a_Z.output_mode="comb_only";
defparam q_39_17_0_a_Z.lut_mask="008f";
defparam q_39_17_0_a_Z.synch_mode="off";
defparam q_39_17_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_28_0_a1_0 (
	.combout(q_39_28_0_a1),
	.dataa(q_39_28_0_a1_a),
	.datab(q_add3),
	.datac(q_add4),
	.datad(q_add5)
);
defparam q_39_28_0_a1_0.operation_mode="normal";
defparam q_39_28_0_a1_0.output_mode="comb_only";
defparam q_39_28_0_a1_0.lut_mask="5d00";
defparam q_39_28_0_a1_0.synch_mode="off";
defparam q_39_28_0_a1_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_28_0_a1_a_Z (
	.combout(q_39_28_0_a1_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add4)
);
defparam q_39_28_0_a1_a_Z.operation_mode="normal";
defparam q_39_28_0_a1_a_Z.output_mode="comb_only";
defparam q_39_28_0_a1_a_Z.lut_mask="5867";
defparam q_39_28_0_a1_a_Z.synch_mode="off";
defparam q_39_28_0_a1_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_34_0_0 (
	.combout(q_39_34_0),
	.dataa(q_39_34_0_a),
	.datab(q_add3),
	.datac(q_add4),
	.datad(q_39_32_0)
);
defparam q_39_34_0_0.operation_mode="normal";
defparam q_39_34_0_0.output_mode="comb_only";
defparam q_39_34_0_0.lut_mask="c505";
defparam q_39_34_0_0.synch_mode="off";
defparam q_39_34_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_34_0_a_Z (
	.combout(q_39_34_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_34_0_a_Z.operation_mode="normal";
defparam q_39_34_0_a_Z.output_mode="comb_only";
defparam q_39_34_0_a_Z.lut_mask="4d58";
defparam q_39_34_0_a_Z.synch_mode="off";
defparam q_39_34_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_48_0_0 (
	.combout(q_39_48_0),
	.dataa(q_39_48_0_a),
	.datab(q_add3),
	.datac(q_add4),
	.datad(q_39_44_0)
);
defparam q_39_48_0_0.operation_mode="normal";
defparam q_39_48_0_0.output_mode="comb_only";
defparam q_39_48_0_0.lut_mask="bdb1";
defparam q_39_48_0_0.synch_mode="off";
defparam q_39_48_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_48_0_a_Z (
	.combout(q_39_48_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_48_0_a_Z.operation_mode="normal";
defparam q_39_48_0_a_Z.output_mode="comb_only";
defparam q_39_48_0_a_Z.lut_mask="1360";
defparam q_39_48_0_a_Z.synch_mode="off";
defparam q_39_48_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_52_0_0 (
	.combout(q_39_52_0),
	.dataa(q_39_52_0_a),
	.datab(q_add3),
	.datac(q_add4),
	.datad(q_39_44_0)
);
defparam q_39_52_0_0.operation_mode="normal";
defparam q_39_52_0_0.output_mode="comb_only";
defparam q_39_52_0_0.lut_mask="7d4d";
defparam q_39_52_0_0.synch_mode="off";
defparam q_39_52_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_52_0_a_Z (
	.combout(q_39_52_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_52_0_a_Z.operation_mode="normal";
defparam q_39_52_0_a_Z.output_mode="comb_only";
defparam q_39_52_0_a_Z.lut_mask="0c6f";
defparam q_39_52_0_a_Z.synch_mode="off";
defparam q_39_52_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_84_a0_0 (
	.combout(q_39_84_a0),
	.dataa(q_39_84_a0_a),
	.datab(q_add3),
	.datac(q_add4),
	.datad(q_add5)
);
defparam q_39_84_a0_0.operation_mode="normal";
defparam q_39_84_a0_0.output_mode="comb_only";
defparam q_39_84_a0_0.lut_mask="002b";
defparam q_39_84_a0_0.synch_mode="off";
defparam q_39_84_a0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_84_a0_a_Z (
	.combout(q_39_84_a0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add4)
);
defparam q_39_84_a0_a_Z.operation_mode="normal";
defparam q_39_84_a0_a_Z.output_mode="comb_only";
defparam q_39_84_a0_a_Z.lut_mask="787f";
defparam q_39_84_a0_a_Z.synch_mode="off";
defparam q_39_84_a0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_101_0 (
	.combout(q_39_101),
	.dataa(q_39_101_a),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add4)
);
defparam q_39_101_0.operation_mode="normal";
defparam q_39_101_0.output_mode="comb_only";
defparam q_39_101_0.lut_mask="429d";
defparam q_39_101_0.synch_mode="off";
defparam q_39_101_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_101_a_Z (
	.combout(q_39_101_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_101_a_Z.operation_mode="normal";
defparam q_39_101_a_Z.output_mode="comb_only";
defparam q_39_101_a_Z.lut_mask="00e1";
defparam q_39_101_a_Z.synch_mode="off";
defparam q_39_101_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_107_a_0 (
	.combout(q_39_107_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_107_a_0.operation_mode="normal";
defparam q_39_107_a_0.output_mode="comb_only";
defparam q_39_107_a_0.lut_mask="30f7";
defparam q_39_107_a_0.synch_mode="off";
defparam q_39_107_a_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_40_0_0 (
	.combout(q_39_40_0),
	.dataa(q_39_40_0_a),
	.datab(q_add0),
	.datac(q_add2),
	.datad(q_add4)
);
defparam q_39_40_0_0.operation_mode="normal";
defparam q_39_40_0_0.output_mode="comb_only";
defparam q_39_40_0_0.lut_mask="5c28";
defparam q_39_40_0_0.synch_mode="off";
defparam q_39_40_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_40_0_a_Z (
	.combout(q_39_40_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add3),
	.datad(q_add4)
);
defparam q_39_40_0_a_Z.operation_mode="normal";
defparam q_39_40_0_a_Z.output_mode="comb_only";
defparam q_39_40_0_a_Z.lut_mask="360c";
defparam q_39_40_0_a_Z.synch_mode="off";
defparam q_39_40_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_72_0_0 (
	.combout(q_39_72_0),
	.dataa(q_39_72_0_a),
	.datab(q_add2),
	.datac(q_add3),
	.datad(q_add4)
);
defparam q_39_72_0_0.operation_mode="normal";
defparam q_39_72_0_0.output_mode="comb_only";
defparam q_39_72_0_0.lut_mask="256f";
defparam q_39_72_0_0.synch_mode="off";
defparam q_39_72_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_72_0_a_Z (
	.combout(q_39_72_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add3),
	.datad(q_add4)
);
defparam q_39_72_0_a_Z.operation_mode="normal";
defparam q_39_72_0_a_Z.output_mode="comb_only";
defparam q_39_72_0_a_Z.lut_mask="1670";
defparam q_39_72_0_a_Z.synch_mode="off";
defparam q_39_72_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_23_0_0 (
	.combout(q_39_23_0),
	.dataa(q_39_23_0_a),
	.datab(q_add1),
	.datac(q_add3),
	.datad(q_add4)
);
defparam q_39_23_0_0.operation_mode="normal";
defparam q_39_23_0_0.output_mode="comb_only";
defparam q_39_23_0_0.lut_mask="3f66";
defparam q_39_23_0_0.synch_mode="off";
defparam q_39_23_0_0.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_23_0_a_Z (
	.combout(q_39_23_0_a),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2)
);
defparam q_39_23_0_a_Z.operation_mode="normal";
defparam q_39_23_0_a_Z.output_mode="comb_only";
defparam q_39_23_0_a_Z.lut_mask="0707";
defparam q_39_23_0_a_Z.synch_mode="off";
defparam q_39_23_0_a_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_56_0_Z (
	.combout(q_39_56_0),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_56_0_Z.operation_mode="normal";
defparam q_39_56_0_Z.output_mode="comb_only";
defparam q_39_56_0_Z.lut_mask="6780";
defparam q_39_56_0_Z.synch_mode="off";
defparam q_39_56_0_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_59_0_Z (
	.combout(q_39_59_0),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_59_0_Z.operation_mode="normal";
defparam q_39_59_0_Z.output_mode="comb_only";
defparam q_39_59_0_Z.lut_mask="f155";
defparam q_39_59_0_Z.synch_mode="off";
defparam q_39_59_0_Z.sum_lutc_input="datac";
// @12:117
  stratix_lcell q_39_62_0_0 (
	.combout(q_39_62_0),
	.dataa(q_add0),
	.datab(q_add1),
	.datac(q_add2),
	.datad(q_add3)
);
defparam q_39_62_0_0.operation_mode="normal";
defparam q_39_62_0_0.output_mode="comb_only";
defparam q_39_62_0_0.lut_mask="551f";