generator_mux.vhd

来自「FPGA开发光盘各章节实例的设计工程与源码」· VHDL 代码 · 共 40 行

------------------------------------------------------------------------------------
-- DESCRIPTION   :  Multiplexer
--                  Code style: used case statement
--                  Width of output terminal: 8
--                  Number of terminals: 1
--                  Output value of all bits when enable not active: '0'
-- 
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_mux is
	port (
		I0 : in std_logic_vector (7 downto 0);
		I1 : in std_logic_vector (7 downto 0);
		S : in std_logic;
		O : out std_logic_vector (7 downto 0)
	);
end entity;



architecture mux_arch of generator_mux is
begin

	process (S, I0)
	begin
		if (S = '0') then
			 O <= I0;
		else
			 O <= I1;
		end if;
	end process;

end architecture;