generator.srs

FPGA开发光盘各章节实例的设计工程与源码

#
#
#
# Created by Synplify VHDL Compiler version Compilers 7.3, Build 073R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sat Jul 16 14:41:43 2005
#
#
#OPTIONS:"|-top|generator|-ram|-fixsmult|-dspmac|-autosm|-fid2|-sharing|on|-encrypt|-ui|-lite|-pro|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\bin\\c_vhdl.exe":1054273098l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\location.map":1054275904l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\std.vhd":1044941154l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\std.vhd":1044941154l
#CUR:"D:\\924lyj\\924\\generator_sin.vhd":1120984208l
#CUR:"D:\\924lyj\\924\\generator_sin.vhd":1120984208l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\std1164.vhd":1044607728l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\std1164.vhd":1044607728l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\arith.vhd":1044607728l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\arith.vhd":1044607728l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\unsigned.vhd":1044607728l
#CUR:"C:\\Program Files\\synplicity\\Synplify_73\\lib\\vhd\\unsigned.vhd":1044607728l
#CUR:"D:\\924lyj\\924\\generator_acc6.vhd":1120984096l
#CUR:"D:\\924lyj\\924\\generator_acc6.vhd":1120984096l
#CUR:"D:\\924lyj\\924\\generator_adder.vhd":1120984152l
#CUR:"D:\\924lyj\\924\\generator_adder.vhd":1120984152l
#CUR:"D:\\924lyj\\924\\generator_and2.vhd":1120984174l
#CUR:"D:\\924lyj\\924\\generator_and2.vhd":1120984174l
#CUR:"D:\\924lyj\\924\\generator_mux.vhd":1120984132l
#CUR:"D:\\924lyj\\924\\generator_mux.vhd":1120984132l
#CUR:"D:\\924lyj\\924\\generator_reg6.vhd":1120984228l
#CUR:"D:\\924lyj\\924\\generator_reg6.vhd":1120984228l
#CUR:"D:\\924lyj\\924\\generator_reg8.vhd":1120984250l
#CUR:"D:\\924lyj\\924\\generator_reg8.vhd":1120984250l
#CUR:"D:\\924lyj\\924\\generator.vhd":1120984040l
#CUR:"D:\\924lyj\\924\\generator.vhd":1120984040l
f "C:\Program Files\synplicity\Synplify_73\lib\vhd\std.vhd"; # file 0
f "D:\924lyj\924\generator_sin.vhd"; # file 1
f "C:\Program Files\synplicity\Synplify_73\lib\vhd\std1164.vhd"; # file 2
f "C:\Program Files\synplicity\Synplify_73\lib\vhd\arith.vhd"; # file 3
f "C:\Program Files\synplicity\Synplify_73\lib\vhd\unsigned.vhd"; # file 4
f "D:\924lyj\924\generator_acc6.vhd"; # file 5
f "D:\924lyj\924\generator_adder.vhd"; # file 6
f "D:\924lyj\924\generator_and2.vhd"; # file 7
f "D:\924lyj\924\generator_mux.vhd"; # file 8
f "D:\924lyj\924\generator_reg6.vhd"; # file 9
f "D:\924lyj\924\generator_reg8.vhd"; # file 10
f "D:\924lyj\924\generator.vhd"; # file 11
@E
@ 
ftell;
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y--------------------------------- 
@
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-y---------------------------------

@ 
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--@
 

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--@
 

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y--------------------------------- 
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