flatsch.sxr

FPGA开发光盘各章节实例的设计工程与源码

BeginView generator NoName
Inst: Q_out[6]   Q_out_6_ stratix_io_PD0 
Inst: Q_out[5]   Q_out_5_ stratix_io_PD0 
Inst: Q_out[4]   Q_out_4_ stratix_io_PD0 
Inst: Q_out[3]   Q_out_3_ stratix_io_PD0 
Inst: Q_out[2]   Q_out_2_ stratix_io_PD0 
Inst: Q_out[1]   Q_out_1_ stratix_io_PD0 
Inst: Q_out[0]   Q_out_0_ stratix_io_PD0 
Inst: DATA_in[5]   DATA_in_5_ stratix_io_OP0 
Inst: DATA_in[4]   DATA_in_4_ stratix_io_OP0 
Inst: DATA_in[3]   DATA_in_3_ stratix_io_OP0 
Inst: DATA_in[2]   DATA_in_2_ stratix_io_OP0 
Inst: DATA_in[1]   DATA_in_1_ stratix_io_OP0 
Inst: DATA_in[0]   DATA_in_0_ stratix_io_OP0 
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Inst: U3.q_add3   U3.q_add3_0 a1077_9696_E8E8 
Inst: U3.q_add2   U3.q_add2_0 a1077_9696_E8E8 
Inst: U3.q_add1   U3.q_add1_0 a1077_9696_E8E8 
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Inst: U2.Q[2]   U2.Q_2_ a21329_A0A0 
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Inst: U2.Q[4]   U2.Q_4_ a21329_A0A0 
Inst: U2.Q[5]   U2.Q_5_ a21329_A0A0 
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Inst: U6.q_39_107_a   U6.q_39_107_a_0 a241_30F7 
Inst: U6.q_39_40_0   U6.q_39_40_0_0 a241_5C28 
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Inst: U6.q_39_72_0   U6.q_39_72_0_0 a241_256F 
Inst: U6.q_39_72_0_a   U6.q_39_72_0_a_Z a241_1670 
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Inst: U6.q_39_62_0   U6.q_39_62_0_0 a241_551F 
Inst: U6.q_39_64_0   U6.q_39_64_0_0 a241_03CD 
Inst: U6.q_39_95   U6.q_39_95_0 a241_06AF 
Inst: U6.q_39_98   U6.q_39_98_0 a241_019F 
Inst: U6.q_39_32_0   U6.q_39_32_0_Z a113_2424 
Inst: U6.q_39_44_0   U6.q_39_44_0_Z a113_2929 
Inst: U1.Q[4]   U1.Q_4_ ff4994_FF00 
Inst: U1.Q[3]   U1.Q_3_ ff4994_FF00 
Inst: U1.Q[2]   U1.Q_2_ ff4994_FF00 
Inst: U1.Q[1]   U1.Q_1_ ff4994_FF00 
Inst: U1.Q[0]   U1.Q_0_ ff4994_FF00 
Net:  U7.Q[7]   U7_Q[7] 
Net:  U7.Q[6]   U7_Q[6] 
Net:  U7.Q[5]   U7_Q[5] 
Net:  U7.Q[4]   U7_Q[4] 
Net:  U7.Q[3]   U7_Q[3] 
Net:  U7.Q[2]   U7_Q[2] 
Net:  U7.Q[1]   U7_Q[1] 
Net:  U7.Q[0]   U7_Q[0] 
Net:  U1.Q[0]   U1_Q[0] 
Net:  U1.Q[1]   U1_Q[1] 
Net:  U1.Q[2]   U1_Q[2] 
Net:  U1.Q[3]   U1_Q[3] 
Net:  U1.Q[4]   U1_Q[4] 
Net:  U1.Q[5]   U1_Q[5] 
Net:  U9.O_0_and2   U9_O_0_and2 
Net:  U6.q_39_98   U6_q_39_98 
Net:  U6.q_39_95   U6_q_39_95 
Net:  U6.q_39_64_0   U6_q_39_64_0 
Net:  U6.q_39_62_0   U6_q_39_62_0 
Net:  U6.q_39_23_0   U6_q_39_23_0 
Net:  U6.q_39_72_0   U6_q_39_72_0 
Net:  U6.q_39_40_0   U6_q_39_40_0 
Net:  U6.q_39_107_a   U6_q_39_107_a 
Net:  U6.q_39_101   U6_q_39_101 
Net:  U6.q_39_84_a0   U6_q_39_84_a0 
Net:  U6.q_39_52_0   U6_q_39_52_0 
Net:  U6.q_39_48_0   U6_q_39_48_0 
Net:  U6.q_39_34_0   U6_q_39_34_0 
Net:  U6.q_39_28_0_a1   U6_q_39_28_0_a1 
Net:  U3.q_add3   U3_q_add3 
Net:  U3.q_add2   U3_q_add2 
Net:  U3.q_add1   U3_q_add1 
Net:  U3.q_add0   U3_q_add0 
Net:  U6.q_39_17_0   U6_q_39_17_0 
Net:  U3.q_add4   U3_q_add4 
Net:  U3.q_add5   U3_q_add5 
Net:  U6.q_39_66_0_c   U6_q_39_66_0_c 
Net:  U4.un1_a_0_and2[0]   U4_un1_a_0_and2[0] 
Net:  U4.un1_a_0_and2[1]   U4_un1_a_0_and2[1] 
Net:  U4.un1_a_0_and2[2]   U4_un1_a_0_and2[2] 
Net:  U4.un1_a_0_and2[3]   U4_un1_a_0_and2[3] 
Net:  U4.un1_a_0_and2[4]   U4_un1_a_0_and2[4] 
Net:  U4.un1_a_0_and2[5]   U4_un1_a_0_and2[5] 
Net:  U8.O_0_and2   U8_O_0_and2 
Net:  U4.Q[0]   U4_Q[0] 
Net:  U4.Q[1]   U4_Q[1] 
Net:  U4.Q[2]   U4_Q[2] 
Net:  U4.Q[3]   U4_Q[3] 
Net:  U4.Q[4]   U4_Q[4] 
Net:  U4.Q[5]   U4_Q[5] 
EndView generator NoName

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