📄 generator.srr
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$ Start of Compile
#Sat Jul 16 15:28:31 2005
Synplicity VHDL Compiler, version Compilers 7.3, Build 073R, built May 30 2003
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
VHDL syntax check successful!
Compiler output is up to date. No re-compile necessary
Synthesizing work.generator.generator_arch
Synthesizing work.generator_and2.and_angen_arch
Post processing for work.generator_and2.and_angen_arch
Synthesizing work.generator_reg8.reg_arch8
Post processing for work.generator_reg8.reg_arch8
Synthesizing work.generator_acc6.acc_arch
Post processing for work.generator_acc6.acc_arch
Synthesizing work.generator_adder.add_angen_arch
Post processing for work.generator_adder.add_angen_arch
Synthesizing work.generator_reg6.reg_arch6
Post processing for work.generator_reg6.reg_arch6
Synthesizing work.generator_sin.sin_arch
Post processing for work.generator_sin.sin_arch
Post processing for work.generator.generator_arch
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Altera Technology Mapper, version 7.3, Build 173R, built Jun 10 2003
Copyright (C) 1994-2003, Synplicity Inc. All Rights Reserved
Running FSM Explorer ...
Did not find any FSM for encoding selection. Exiting ...
FSM Explorer successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Altera Technology Mapper, version 7.3, Build 173R, built Jun 10 2003
Copyright (C) 1994-2003, Synplicity Inc. All Rights Reserved
Automatic dissolve at startup in view:work.generator(generator_arch) of U9(generator_and2)
Automatic dissolve at startup in view:work.generator(generator_arch) of U8(generator_and2)
Automatic dissolve at startup in view:work.generator(generator_arch) of U7(generator_reg8)
Automatic dissolve at startup in view:work.generator(generator_arch) of U4(generator_acc6)
Automatic dissolve at startup in view:work.generator(generator_arch) of U3(generator_adder)
Automatic dissolve at startup in view:work.generator(generator_arch) of U2(generator_reg6)
Automatic dissolve at startup in view:work.generator(generator_arch) of U1(generator_reg6)
@N:"d:\924lyj\924\generator_sin.vhd":30:3:30:6|Found ROM, 'q_39[7:0]', 64 words by 8 bits
Writing Analyst data base F:\xudong\mybook1\cht5\sypl\exp1\generator.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to F:\xudong\mybook1\cht5\sypl\exp1\generator.xrf
Found clock generator|CLK with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Sat Jul 16 15:28:36 2005
#
Top view: generator
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: 994.665
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------
generator|CLK 1.0 MHz 187.4 MHz 1000.000 5.335 994.665 inferred default_clkgroup
====================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------
generator|CLK generator|CLK | 1000.000 994.665 | No paths - | No paths - | No paths -
======================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: generator|CLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------
U1.Q[0] generator|CLK stratix_lcell_ff regout Q_0 0.156 994.665
U4.Q[0] generator|CLK stratix_lcell_ff regout Q_0 0.156 994.665
U1.Q[1] generator|CLK stratix_lcell_ff regout Q_1 0.156 994.740
U4.Q[1] generator|CLK stratix_lcell_ff regout Q_1 0.156 994.740
U1.Q[2] generator|CLK stratix_lcell_ff regout Q_2 0.156 994.774
U4.Q[2] generator|CLK stratix_lcell_ff regout Q_2 0.156 994.774
U1.Q[3] generator|CLK stratix_lcell_ff regout Q_3 0.156 994.945
U4.Q[3] generator|CLK stratix_lcell_ff regout Q_3 0.156 994.945
U1.Q[4] generator|CLK stratix_lcell_ff regout Q_4 0.156 995.787
U4.Q[4] generator|CLK stratix_lcell_ff regout Q_4 0.156 995.873
==========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
U7.Q[0] generator|CLK stratix_lcell_ff datab q_39_17_0 999.551 994.665
U7.Q[1] generator|CLK stratix_lcell_ff datab q_39_23_0 999.551 994.665
U7.Q[2] generator|CLK stratix_lcell_ff datab q_39_40_0 999.551 994.665
U7.Q[3] generator|CLK stratix_lcell_ff datab q_39_52_0 999.551 994.665
U7.Q[5] generator|CLK stratix_lcell_ff datab q_39_72_0 999.551 994.665
U7.Q[6] generator|CLK stratix_lcell_ff datab q_39_84_a0 999.551 994.665
U7.Q[0] generator|CLK stratix_lcell_ff datac q_39_101 999.648 994.762
U7.Q[1] generator|CLK stratix_lcell_ff datac q_39_28_0_a1 999.648 994.762
U7.Q[2] generator|CLK stratix_lcell_ff datac q_39_34_0 999.648 994.762
U7.Q[3] generator|CLK stratix_lcell_ff datac q_39_48_0 999.648 994.762
===================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.449
= Required time: 999.551
- Propagation time: 4.886
= Slack (critical) : 994.665
Number of logic level(s): 4
Starting point: U1.Q[0] / regout
Ending point: U7.Q[0] / datab
The start point is clocked by generator|CLK [rising] on pin clk
The end point is clocked by generator|CLK [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------
U1.Q[0] stratix_lcell_ff regout Out 0.156 0.156 -
Q_0 Net - - 0.800 - 1
U3.q_add0 stratix_lcell dataa In - 0.956 -
U3.q_add0 stratix_lcell cout Out 0.610 1.566 -
q_carry_0 Net - - 0.000 - 1
U3.q_add1 stratix_lcell cin In - 1.566 -
U3.q_add1 stratix_lcell combout Out 0.598 2.164 -
q_add1 Net - - 1.183 - 22
U6.q_39_17_0_a stratix_lcell datab In - 3.347 -
U6.q_39_17_0_a stratix_lcell combout Out 0.280 3.627 -
q_39_17_0_a Net - - 0.446 - 1
U6.q_39_17_0 stratix_lcell dataa In - 4.074 -
U6.q_39_17_0 stratix_lcell combout Out 0.366 4.440 -
q_39_17_0 Net - - 0.446 - 1
U7.Q[0] stratix_lcell_ff datab In - 4.886 -
============================================================================================
Total path delay (propagation time + setup) of 5.335 is 2.459(46.1%) logic and 2.876(53.9%) route.
##### END OF TIMING REPORT #####]
##### START OF AREA REPORT #####[
Design view:work.generator(generator_arch)
Selecting part EP1S25F780C5
@N| The following device usage report estimates place and route data. Please look at the place and route report for final resource usage.
I/O ATOMs: 19
Total LUTs: 64 of 25660 ( 0%)
Logic resources: 64 ATOMs of 25660 ( 0%)
ATOM count by mode:
normal: 54
arithmetic: 10
DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 2)
M4Ks: 0 (0% of 138)
M512s: 0 (0% of 224)
Total ESB: 0 bits
ATOMs using regout pin: 20
also using enable pin: 14
also using combout pin: 0
ATOMs using combout pin: 44
Number of Inputs on ATOMs: 271
Number of Nets: 243
##### END OF AREA REPORT #####]
Mapper successful!
Process took 0h:0m:3s realtime, 0h:0m:3s cputime
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