generator_sin.vhd

FPGA开发光盘各章节实例的设计工程与源码

------------------------------------------------------------------------------------
-- DESCRIPTION   :  Name : Analog Generator ROM
-- 
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity generator_sin is
    port (
	OE : in STD_LOGIC;
	ADDRESS : in STD_LOGIC_VECTOR(5 downto 0);
	Q : out STD_LOGIC_VECTOR(7 downto 0) );

end generator_sin;



architecture sin_arch of generator_sin is 

begin 
	process(ADDRESS, OE)
	begin
		if (OE = '1') then 
			case (ADDRESS) is 
				when "000000" => Q <= CONV_STD_LOGIC_VECTOR(0,8);
				when "000001" => Q <= CONV_STD_LOGIC_VECTOR(1,8);
				when "000010" => Q <= CONV_STD_LOGIC_VECTOR(3,8);
				when "000011" => Q <= CONV_STD_LOGIC_VECTOR(5,8);
				when "000100" => Q <= CONV_STD_LOGIC_VECTOR(7,8);
				when "000101" => Q <= CONV_STD_LOGIC_VECTOR(10,8);
				when "000110" => Q <= CONV_STD_LOGIC_VECTOR(13,8);
				when "000111" => Q <= CONV_STD_LOGIC_VECTOR(17,8);
				when "001000" => Q <= CONV_STD_LOGIC_VECTOR(21,8);
				when "001001" => Q <= CONV_STD_LOGIC_VECTOR(25,8);
				when "001010" => Q <= CONV_STD_LOGIC_VECTOR(31,8);
				when "001011" => Q <= CONV_STD_LOGIC_VECTOR(37,8);
				when "001100" => Q <= CONV_STD_LOGIC_VECTOR(43,8);
				when "001101" => Q <= CONV_STD_LOGIC_VECTOR(51,8);
				when "001110" => Q <= CONV_STD_LOGIC_VECTOR(60,8);
				when "001111" => Q <= CONV_STD_LOGIC_VECTOR(72,8);
				when "010000" => Q <= CONV_STD_LOGIC_VECTOR(85,8);
				when "010001" => Q <= CONV_STD_LOGIC_VECTOR(100,8);
				when "010010" => Q <= CONV_STD_LOGIC_VECTOR(116,8);
				when "010011" => Q <= CONV_STD_LOGIC_VECTOR(132,8);
				when "010100" => Q <= CONV_STD_LOGIC_VECTOR(148,8);
				when "010101" => Q <= CONV_STD_LOGIC_VECTOR(164,8);
				when "010110" => Q <= CONV_STD_LOGIC_VECTOR(180,8);
				when "010111" => Q <= CONV_STD_LOGIC_VECTOR(196,8);
				when "011000" => Q <= CONV_STD_LOGIC_VECTOR(212,8);
				when "011001" => Q <= CONV_STD_LOGIC_VECTOR(228,8);
				when "011010" => Q <= CONV_STD_LOGIC_VECTOR(234,8);
				when "011011" => Q <= CONV_STD_LOGIC_VECTOR(238,8);
				when "011100" => Q <= CONV_STD_LOGIC_VECTOR(244,8);
				when "011101" => Q <= CONV_STD_LOGIC_VECTOR(248,8);
				when "011110" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
				when "011111" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
				when "100000" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
				when "100001" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
				when "100010" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
				when "100011" => Q <= CONV_STD_LOGIC_VECTOR(248,8);
				when "100100" => Q <= CONV_STD_LOGIC_VECTOR(244,8);
				when "100101" => Q <= CONV_STD_LOGIC_VECTOR(238,8);
				when "100110" => Q <= CONV_STD_LOGIC_VECTOR(234,8);
				when "100111" => Q <= CONV_STD_LOGIC_VECTOR(228,8);
				when "101000" => Q <= CONV_STD_LOGIC_VECTOR(212,8);
				when "101001" => Q <= CONV_STD_LOGIC_VECTOR(196,8);
				when "101010" => Q <= CONV_STD_LOGIC_VECTOR(180,8);
				when "101011" => Q <= CONV_STD_LOGIC_VECTOR(164,8);
				when "101100" => Q <= CONV_STD_LOGIC_VECTOR(148,8);
				when "101101" => Q <= CONV_STD_LOGIC_VECTOR(132,8);
				when "101110" => Q <= CONV_STD_LOGIC_VECTOR(116,8);
				when "101111" => Q <= CONV_STD_LOGIC_VECTOR(100,8);
				when "110000" => Q <= CONV_STD_LOGIC_VECTOR(85,8);
				when "110001" => Q <= CONV_STD_LOGIC_VECTOR(72,8);
				when "110010" => Q <= CONV_STD_LOGIC_VECTOR(60,8);
				when "110011" => Q <= CONV_STD_LOGIC_VECTOR(51,8);
				when "110100" => Q <= CONV_STD_LOGIC_VECTOR(43,8);
				when "110101" => Q <= CONV_STD_LOGIC_VECTOR(37,8);
				when "110110" => Q <= CONV_STD_LOGIC_VECTOR(31,8);
				when "110111" => Q <= CONV_STD_LOGIC_VECTOR(25,8);
				when "111000" => Q <= CONV_STD_LOGIC_VECTOR(21,8);
				when "111001" => Q <= CONV_STD_LOGIC_VECTOR(17,8);
				when "111010" => Q <= CONV_STD_LOGIC_VECTOR(13,8);
				when "111011" => Q <= CONV_STD_LOGIC_VECTOR(10,8);
				when "111100" => Q <= CONV_STD_LOGIC_VECTOR(7,8);
				when "111101" => Q <= CONV_STD_LOGIC_VECTOR(5,8);
				when "111110" => Q <= CONV_STD_LOGIC_VECTOR(3,8);
				when "111111" => Q <= CONV_STD_LOGIC_VECTOR(0,8);
				when others => Q <= "00000000";
			end case;
		else
			Q <= "ZZZZZZZZ"; 
		end if;
	end process;
end architecture sin_arch;