generator.vht

FPGA开发光盘各章节实例的设计工程与源码

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors     
-- are exported from a vector file in the Quartus Waveform Editor and apply to  
-- the top level entity of the current Quartus project .The user can use this   
-- testbench to simulate his design using a third-party simulation tool .       
-- *****************************************************************************
-- Generated on "07/16/2005 11:13:01"
                                                             
-- Vhdl Test Bench(with test vectors) for design  :          generator
-- 
-- Simulation tool : 3rd Party
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY generator_vhd_vec_tst IS
END generator_vhd_vec_tst;
ARCHITECTURE generator_arch OF generator_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL t_sig_CE : STD_LOGIC;
SIGNAL t_sig_CLK : STD_LOGIC;
SIGNAL t_sig_CLR : STD_LOGIC;
SIGNAL t_sig_DATA : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL t_sig_FR : STD_LOGIC;
SIGNAL t_sig_PR : STD_LOGIC;
SIGNAL t_sig_Q : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT generator
	PORT (
	CE : IN STD_LOGIC;
	CLK : IN STD_LOGIC;
	CLR : IN STD_LOGIC;
	DATA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
	FR : IN STD_LOGIC;
	PR : IN STD_LOGIC;
	Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	tb : generator
	PORT MAP (
-- list connections between master ports and signals
	CE => t_sig_CE,
	CLK => t_sig_CLK,
	CLR => t_sig_CLR,
	DATA => t_sig_DATA,
	FR => t_sig_FR,
	PR => t_sig_PR,
	Q => t_sig_Q
	);

-- CLK
t_prcs_CLK: PROCESS
BEGIN
LOOP
	t_sig_CLK <= '0';
	WAIT FOR 2500 ps;
	t_sig_CLK <= '1';
	WAIT FOR 2500 ps;
	IF (NOW > 10000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_CLK;

-- CLR
t_prcs_CLR: PROCESS
BEGIN
	t_sig_CLR <= '0';
	WAIT FOR 75000 ps;
	t_sig_CLR <= '1';
	WAIT FOR 190000 ps;
	t_sig_CLR <= '0';
WAIT;
END PROCESS t_prcs_CLR;

-- CE
t_prcs_CE: PROCESS
BEGIN
	t_sig_CE <= '0';
	WAIT FOR 385000 ps;
	t_sig_CE <= '1';
	WAIT FOR 9600000 ps;
	t_sig_CE <= '0';
WAIT;
END PROCESS t_prcs_CE;
-- DATA[5]
t_prcs_DATA_5: PROCESS
BEGIN
	t_sig_DATA(5) <= '0';
	WAIT FOR 4955000 ps;
	t_sig_DATA(5) <= '1';
	WAIT FOR 320000 ps;
	FOR i IN 1 TO 7
	LOOP
		t_sig_DATA(5) <= '0';
		WAIT FOR 320000 ps;
		t_sig_DATA(5) <= '1';
		WAIT FOR 320000 ps;
	END LOOP;
	t_sig_DATA(5) <= '0';
WAIT;
END PROCESS t_prcs_DATA_5;
-- DATA[4]
t_prcs_DATA_4: PROCESS
BEGIN
	t_sig_DATA(4) <= '0';
	WAIT FOR 4795000 ps;
	t_sig_DATA(4) <= '1';
	WAIT FOR 160000 ps;
	FOR i IN 1 TO 15
	LOOP
		t_sig_DATA(4) <= '0';
		WAIT FOR 160000 ps;
		t_sig_DATA(4) <= '1';
		WAIT FOR 160000 ps;
	END LOOP;
	t_sig_DATA(4) <= '0';
	WAIT FOR 160000 ps;
	t_sig_DATA(4) <= '1';
WAIT;
END PROCESS t_prcs_DATA_4;
-- DATA[3]
t_prcs_DATA_3: PROCESS
BEGIN
	t_sig_DATA(3) <= '0';
	WAIT FOR 4715000 ps;
	t_sig_DATA(3) <= '1';
	WAIT FOR 80000 ps;
	FOR i IN 1 TO 32
	LOOP
		t_sig_DATA(3) <= '0';
		WAIT FOR 80000 ps;
		t_sig_DATA(3) <= '1';
		WAIT FOR 80000 ps;
	END LOOP;
	t_sig_DATA(3) <= '0';
	WAIT FOR 80000 ps;
	t_sig_DATA(3) <= '1';
WAIT;
END PROCESS t_prcs_DATA_3;
-- DATA[2]
t_prcs_DATA_2: PROCESS
BEGIN
	t_sig_DATA(2) <= '0';
	WAIT FOR 4675000 ps;
	t_sig_DATA(2) <= '1';
	WAIT FOR 40000 ps;
	FOR i IN 1 TO 66
	LOOP
		t_sig_DATA(2) <= '0';
		WAIT FOR 40000 ps;
		t_sig_DATA(2) <= '1';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_DATA(2) <= '0';
WAIT;
END PROCESS t_prcs_DATA_2;
-- DATA[1]
t_prcs_DATA_1: PROCESS
BEGIN
	t_sig_DATA(1) <= '0';
	WAIT FOR 4655000 ps;
	t_sig_DATA(1) <= '1';
	WAIT FOR 20000 ps;
	FOR i IN 1 TO 133
	LOOP
		t_sig_DATA(1) <= '0';
		WAIT FOR 20000 ps;
		t_sig_DATA(1) <= '1';
		WAIT FOR 20000 ps;
	END LOOP;
	t_sig_DATA(1) <= '0';
WAIT;
END PROCESS t_prcs_DATA_1;
-- DATA[0]
t_prcs_DATA_0: PROCESS
BEGIN
	t_sig_DATA(0) <= '0';
	WAIT FOR 465000 ps;
	t_sig_DATA(0) <= '1';
	WAIT FOR 4170000 ps;
	FOR i IN 1 TO 268
	LOOP
		t_sig_DATA(0) <= '0';
		WAIT FOR 10000 ps;
		t_sig_DATA(0) <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	t_sig_DATA(0) <= '0';
WAIT;
END PROCESS t_prcs_DATA_0;

-- PR
t_prcs_PR: PROCESS
BEGIN
	t_sig_PR <= '0';
	WAIT FOR 4945000 ps;
	t_sig_PR <= '1';
	WAIT FOR 5040000 ps;
	t_sig_PR <= '0';
WAIT;
END PROCESS t_prcs_PR;

-- FR
t_prcs_FR: PROCESS
BEGIN
	t_sig_FR <= '0';
	WAIT FOR 465000 ps;
	t_sig_FR <= '1';
	WAIT FOR 4205000 ps;
	t_sig_FR <= '0';
WAIT;
END PROCESS t_prcs_FR;
END generator_arch;